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[91.159.24.186]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-3991ad7af8csm2429681fa.21.2026.06.11.00.48.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 11 Jun 2026 00:48:34 -0700 (PDT) Message-ID: <00643a25-040a-4bec-8324-f52b30d84f9f@linaro.org> Date: Thu, 11 Jun 2026 10:48:34 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] arm64: dts: qcom: sm8550: add SDHC4 controller node To: William Bright Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ram Boukobza , Tendai Makumire References: <20260427-sm8550-sdhc4-support-v2-1-a4241f43ecd5@imd-tec.com> <5a5cbf8f-07ef-419a-8d30-c1b0b2786312@linaro.org> From: Vladimir Zapolskiy In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 6/10/26 12:59, William Bright wrote: > On Wed, Jun 10, 2026 at 11:21:53AM +0300, Vladimir Zapolskiy wrote: >> FWIW due to https://www.nxp.com/docs/en/data-sheet/IW416.pdf "10.7.1 VIO_SD >> DC characteristics" SDR104 speed mode is not supported by the module, thus >> the selection of the SDR50 speed mode on the host side sounds to be correct >> in your case. >> >> In SDR50 speed mode gcc_sdcc4_apps_clk clock frequency should be exactly >> 100MHz, and since it differs, it has an impact during the tuning phase. >> >> Definitely clk/qcom/gcc-sm8550.c says that the maximum supported frequency >> is 75MHz, the same is found in the downstream v5.15 kernel: >> >> static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { >> F(400000, P_BI_TCXO, 12, 1, 4), >> F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), >> F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0), >> F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), >> { } >> }; >> >> Can you dump CAPS1 register value of SM8550 SDHC4? What does it say about >> SDR50 mode support and need for SDR50 mode tuning? >> >> -- >> Best wishes, >> Vladimir > CAPS0 and CAPS1 are below: > sdhci_msm 8844000.mmc: CAPS0: 0x3029c8b2 CAPS1: 0x0000a08b > For CAPS1: > Bit 0 (SDR50 support) = 1 > Bit 13 (Use Tuning for SDR50) = 1 > It looks to report that SDR50 is supported with tuning required. > Looks like the SDHC driver behaves expectedly then. For me it's hard to say what may be the rootcause, I believe the lower bus frequency should be fine, so it sounds like a hardware issue, but could it be PCB/board specific one? If you find a chance to copy the SDHC driver (and its small dependencies) from Android and test it on your board, and if it also fails, then it might be well concluded that something is wrong with hardware, still it won't be quite convincing that the SoC SDHC is to blame here. Hope it helps. -- Best wishes, Vladimir