From: "Gerard Kam" <gerardk5@verizon.net>
To: "'Haavard Skinnemoen'" <haavard.skinnemoen@atmel.com>
Cc: "'David Brownell'" <david-b@pacbell.net>,
<spi-devel-general@lists.sourceforge.net>,
"'Lars Steubesand'" <lars.steubesand@philips.com>,
<linux-kernel@vger.kernel.org>
Subject: RE: [PATCH] atmel_spi: fix hang due to missed interrupt
Date: Fri, 1 Aug 2008 13:07:24 -0700 [thread overview]
Message-ID: <008301c8f412$37dc6b00$2f01a8c0@hobbes> (raw)
In-Reply-To: <20080801154931.120632f1@hskinnemo-gx745.norway.atmel.com>
Hi there
> -----Original Message-----
> From: Haavard Skinnemoen [mailto:haavard.skinnemoen@atmel.com]
> Sent: Friday, August 01, 2008 6:50 AM
>
> Haavard Skinnemoen <haavard.skinnemoen@atmel.com> wrote:
> > spi_writel(as, RNCR, 0);
> > spi_writel(as, TNCR, 0);
> These writes are also completely pointless -- RNCR is zeroed
> automatically after it gets shifted into RCR.
While looking at the patch yesterday I was thinking the same thing. Now it
bugs me that this observation didn't occur when I was working on this
problem. Maybe the code symmetry makes it look "correct".
> Actually, I think the real bug happens right here
You're probably correct. A race condition that intermittently clears a
pending interrupt fits the observed symptom.
> As for the overruns, I'm beginning to suspect that the only way to get
> rid of those and still maintain a reasonable transfer rate is to use
> bounce buffers in faster RAM (e.g. on-chip SRAM).
For my at91sam9260 board, I eliminated one cause of SPI overruns by lowering
the interrupt priorities of the six USARTs (default was 5, changed to 4)
relative to the two SPI controllers (default is 5). The test I used for
this issue is 'ls -lR' on the flash filesystem.
Regards -- Gerard
prev parent reply other threads:[~2008-08-01 20:14 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-07-31 17:10 Haavard Skinnemoen
2008-08-01 13:49 ` Haavard Skinnemoen
2008-08-01 20:07 ` Gerard Kam [this message]
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