From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755420AbbJACk4 (ORCPT ); Wed, 30 Sep 2015 22:40:56 -0400 Received: from smtpbg299.qq.com ([184.105.67.99]:32903 "EHLO smtpbg299.qq.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755342AbbJACkY (ORCPT ); Wed, 30 Sep 2015 22:40:24 -0400 X-QQ-mid: bizesmtp2t1443667152t233t080 X-QQ-SSF: 01100000000000F0FG52 X-QQ-FEAT: QX/rXDl9P1vTWO1X3rTrDPvNN+u68iye1jr4mdMnlr/NgQ8MHF0uv1woNc9pu Cc+x+dYEeka1UCvN8qmQ1vkvpVXTlpi7BZFBjGSL+7DDHF1cLRsLlQni2hmbjfsr2ypu0jg LhQ4tdW6xFvvLYPqCs4P0MpZPtNf4vnWr/c/OwvzMBkLLtEP1LXdQgk3+fT1iQxtP67mrD4 mwl10SsHR1yIVkB4zlfnNkv7bDAcF3HA9ZavFYal5B6sgCMMQWKhslQdC8j7WiEY= X-QQ-GoodBg: 0 From: "yitian" To: "'Mark Brown'" Cc: , , , , , , , References: <006301d0fac4$94eb5890$bec209b0$@tangramtek.com> <20150930181751.GT15635@sirena.org.uk> In-Reply-To: <20150930181751.GT15635@sirena.org.uk> Subject: RE: [RESEND PATCH 1/1] ASoC: dwc: correct irq clear method Date: Thu, 1 Oct 2015 10:39:09 +0800 Message-ID: <00fe01d0fbf2$5a73cba0$0f5b62e0$@tangramtek.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit X-Mailer: Microsoft Outlook 15.0 Thread-Index: AQIKHt/CpmXEXVA/wiQQItktFqm7cwMWr2Tdncrv87A= Content-Language: zh-cn X-QQ-SENDSIZE: 520 X-QQ-FName: 9F03DFE7615B40729644DE3B5A4A7A1A X-QQ-LocalIP: 112.95.241.173 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > From: linux-arm-kernel > [mailto:linux-arm-kernel-bounces@lists.infradead.org] On Behalf Of Mark > Brown > Sent: Thursday, October 1, 2015 2:18 AM > To: yitian > Cc: alsa-devel@alsa-project.org; wsa@the-dreams.de; > linux-kernel@vger.kernel.org; Andrew.Jackson@arm.com; tiwai@suse.com; > lgirdwood@gmail.com; perex@perex.cz; > linux-arm-kernel@lists.infradead.org > Subject: Re: [RESEND PATCH 1/1] ASoC: dwc: correct irq clear method > > On Tue, Sep 29, 2015 at 10:39:00PM +0800, yitian wrote: > > from Designware I2S datasheet, irq is cleared by reading from > > TOR/ROR registers, rather than by writing into them. > > This doesn't apply against current code, please check and resend. Hi Mark: Thanks for your comments. Maybe I misunderstand your meaning. Please correct me. I synced up to latest kernel branch, the code is the same as what this patch was generated. I checked designware I2S spec "version 1.08a June 2014", it specified that the TOR and ROR registers are read only and reading the last bit will clear tx/rx overrun irq. Also I have checked this register by writing its last bit, the overrun irq is not cleared. But if I read the last bit, the overrun irq is cleared. That means the spec is correct. Can you please let me know what else I should double check? Thanks.