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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b55d67d5c2bsm873147966b.37.2025.10.13.01.19.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 13 Oct 2025 01:19:06 -0700 (PDT) Message-ID: <01122bf2-7f8c-4d93-9557-c625b4eac631@oss.qualcomm.com> Date: Mon, 13 Oct 2025 10:19:03 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/9] arm64: dts: qcom: ipq5424: Add QPIC SPI NAND controller support To: Md Sadre Alam , broonie@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, vkoul@kernel.org, linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org Cc: quic_varada@quicinc.com References: <20251008090413.458791-1-quic_mdalam@quicinc.com> <20251008090413.458791-5-quic_mdalam@quicinc.com> <911ee444-25a9-a645-d14f-72fc239e5eb7@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <911ee444-25a9-a645-d14f-72fc239e5eb7@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: MfCD-aQBRLebntwqdFgOZmXtHC7hb3SY X-Proofpoint-ORIG-GUID: MfCD-aQBRLebntwqdFgOZmXtHC7hb3SY X-Authority-Analysis: v=2.4 cv=eaIwvrEH c=1 sm=1 tr=0 ts=68ecb5fc cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=COk6AnOGAAAA:8 a=OlpJZY4RW8OWQeam8GsA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDExMDAyMiBTYWx0ZWRfX3XYLA/f0aera lM4bUXy6ENxFDr1r5Q0Zl9JUIWwwCOIcfSBoFdB1JB2WoWMZEOi2s2984Roj9PSIv1Nli7k9vxR yB6bWRcpQVym9RN5lkaudB/eH6fHtLPEC3T1cvkwDPDE0xjyXoacC/BVvlxVhV/RXRn8QE8qi5n rmcVGHMOA+1hjyb5+dNuMaqlXcjGhTgObDbtkJxZQiufxy6kTZ+TeWvSYGF246kr8vrKTx4+hOa cfz9/k/jrejq7HdW/1KWwsIi+YH80YyftveOOCSQrY+fMtCIWRdYb3TPz9muh6wlLQM6qtbJwdW rQUpnsH/lXd6QUEixxysK9vR09d/YM+iofCiM0eWWypVmP2mE6JeMNPoKs9dgeLCKpqjOi8q6Jl 9pDBCxskaEFwhRnHcGrUzan7cXKw/A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-13_03,2025-10-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 spamscore=0 impostorscore=0 phishscore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510110022 On 10/13/25 8:10 AM, Md Sadre Alam wrote: > > > On 10/8/2025 6:00 PM, Konrad Dybcio wrote: >> On 10/8/25 11:04 AM, Md Sadre Alam wrote: >>> Add device tree nodes for QPIC SPI NAND flash controller support >>> on IPQ5424 SoC. >>> >>> The IPQ5424 SoC includes a QPIC controller that supports SPI NAND flash >>> devices with hardware ECC capabilities and DMA support through BAM >>> (Bus Access Manager). >>> >>> Signed-off-by: Md Sadre Alam >>> --- [...] >> >>> +            dmas = <&qpic_bam 0>, >>> +                   <&qpic_bam 1>, >>> +                   <&qpic_bam 2>; >>> +            dma-names = "tx", "rx", "cmd"; >>> +            status = "disabled"; >> >> Is there anything preventing us from enabling both these nodes by >> default on all boards (maybe secure configuration or required >> regulators)? > We can't enable NAND by default in the common DTSI because the GPIOs are shared between eMMC and NAND.The decision to enable NAND must be made at the board-specific level, depending on the flash type used on that > particular board or RDP.Enabling it globally could lead to conflicts on platforms where eMMC is present. Right, thanks Konrad