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AJvYcCWrrn/nX66dt0GNcMNpUC0pY21qfiygbqQ4MOwVinNBuULSWws82jpV5AOvMvKtO7UXQJCAWpFTS9V12m4=@vger.kernel.org X-Gm-Message-State: AOJu0YxKs25mvyEkNODvS38dDYeaAaXRqv4koBhhSYj6BAkJQEhKM50Y bZYmL7SrxgULh9/EocA7skJVyPA3+BJR7ocgsNXkmRdsQwisWytCfaP1K7Mab5dYOzcyFx2T3Gb A X-Google-Smtp-Source: AGHT+IHcjt49YmGjuMTP6l84E4tCJkuOLW8/54vo4S7Nxntsh06kftkO0W8XYBJzpKPMB1h8yxM1vQ== X-Received: by 2002:a17:907:94c4:b0:a9e:8522:1bd8 with SMTP id a640c23a62f3a-a9eefebd13bmr1574005566b.6.1731393908945; Mon, 11 Nov 2024 22:45:08 -0800 (PST) Received: from [192.168.0.157] ([79.115.63.225]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9ee0defbdcsm676752366b.159.2024.11.11.22.45.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Nov 2024 22:45:08 -0800 (PST) Message-ID: <01160386-a65f-44b0-ac57-ad77754f01cc@linaro.org> Date: Tue, 12 Nov 2024 06:45:06 +0000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] mtd: spi-nor: core: replace dummy buswidth from addr to data To: Cheng Ming Lin Cc: pratyush@kernel.org, mwalle@kernel.org, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, alvinzhou@mxic.com.tw, leoyu@mxic.com.tw, Cheng Ming Lin References: <20241107093016.151448-1-linchengming884@gmail.com> <437e9c87-fbae-4402-858c-ce6de0a992c7@linaro.org> Content-Language: en-US From: Tudor Ambarus In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 11/12/24 2:42 AM, Cheng Ming Lin wrote: > Hi Tudor, > > Tudor Ambarus 於 2024年11月11日 週一 下午6:18寫道： >> >> >> >> On 11/7/24 9:30 AM, Cheng Ming Lin wrote: >>> From: Cheng Ming Lin >>> >>> The default dummy cycle for Macronix SPI NOR flash in Octal Output >>> Read Mode(1-1-8) is 20. >>> >>> Currently, the dummy buswidth is set according to the address bus width. >>> In the 1-1-8 mode, this means the dummy buswidth is 1. When converting >>> dummy cycles to bytes, this results in 20 x 1 / 8 = 2 bytes, causing the >>> host to read data 4 cycles too early. >>> >>> Since the protocol data buswidth is always greater than or equal to the >>> address buswidth. Setting the dummy buswidth to match the data buswidth >>> increases the likelihood that the dummy cycle-to-byte conversion will be >>> divisible, preventing the host from reading data prematurely. >> >> This is still very wrong and the `fix` is working just by chance. >> Consider what happens when one requires 10 dummy cycles. BTW, does this >> fix a real problem, or it's just a theoretical fix? > > In 1-1-8 mode, setting the dummy buswidth to match the data > buswidth ensures a dummy buswidth of 8, which can accommodate > all types of dummy cycles. > > This patch resolves a significant issue in 1-1-8 mode, as described above. > shall we add a fixes tag then, and a cc to stable?