From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 43D6E399003 for ; Sun, 2 Aug 2026 16:13:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785687215; cv=none; b=Hgo1FBS5OS135uYEiN7eOvd5D5OtAh7gQSMbu+dYDDdOXm4saq9RNYa6E4igOnNXde5IUMEZF4n/ZnptpsAzZh7ak9+B2bcd9oZtIzo5JbEAWULIjpi0zXJrh/UaNV7NfN7cte/K9XXTFSNXmVZF2PIqBBJG9BNY2O0k9YP/Ph0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785687215; c=relaxed/simple; bh=SmaHLn88jROFMQ1/0fNpoSHRKhOf2uZ8i1Kj/2ddqKw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=DSkdY0K5YXFwXW/WuxMAPdX74cxnl3HOY1NZGAR1wdWsA6BbDw9Ef6U7X9Zoxv2Pvrjyny8Bk2UeO9qFOCTuDccdFNYgpZoqghPpGtv0TnIsuDH1Zpj4RPwwpQy+j8eQvmamDspXzbP+3bm70s0eQ+uls0+5LYtdKIyIt8ns1Gs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=MFECFT6s; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MFECFT6s" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1785687213; x=1817223213; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SmaHLn88jROFMQ1/0fNpoSHRKhOf2uZ8i1Kj/2ddqKw=; b=MFECFT6shRwRUA4gOTVgfGxFBlKLtXJjFdQ0eY5K2nhrzJz93+s6kAJK xtNdyOdHRVelPblx6bguuERq1o6fLqHlcSpyzYAbTXxZFtWDCejmop7b1 Wa1GcN8KLq8clowA1rK/JuwGfF58+bippkZu4DOYBfFnmZProjWFj9Cv1 3cA8vkye7kZFHVaAZAgxlq4XCP30PR3JgwFzo0V96VaAJG+YjyaWJ7kxv IEbJr4e/WHMA8f1nko8rLBiOGoEHH3HPPaiyZ4hL9nJP+kqwa0hw3OnMz hWwypuzZTUVNzPNeZxP+rn4fN4J94FjAY1P2BBf+FPRnr7tHVym9N6/vb Q==; X-CSE-ConnectionGUID: AexaefDgSgOc2ceJVwvFqQ== X-CSE-MsgGUID: gy/lSNPQTUuF/Jk9nO8SWw== X-IronPort-AV: E=McAfee;i="6800,10657,11863"; a="86361202" X-IronPort-AV: E=Sophos;i="6.25,200,1779174000"; d="scan'208";a="86361202" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Aug 2026 09:13:33 -0700 X-CSE-ConnectionGUID: tp6tyM2UTO6/2wgPPu++AA== X-CSE-MsgGUID: zl/T/5EBSF6K8pU9Q9GAoQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,200,1779174000"; d="scan'208";a="264484002" Received: from chenyu-dev.sh.intel.com ([10.239.62.107]) by orviesa003.jf.intel.com with ESMTP; 02 Aug 2026 09:13:29 -0700 From: Chen Yu To: Reinette Chatre , Tony Luck Cc: Ben Horgan , "James Morse" , Dave Martin , Babu Moger , Fenghua Yu , Borislav Petkov , Thomas Gleixner , "Dave Hansen" , Peter Newman , chen.yu@linux.dev, x86@kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 05/31] x86/resctrl: Parse ACPI CMRC table Date: Mon, 3 Aug 2026 00:03:48 +0800 Message-Id: <0189d930c672498480557c5c16efe42940a06b5e.1785680802.git.yu.c.chen@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The CMRC (Cache Monitoring Registers for CPU Agents Description) sub-table of ERDT describes the MMIO registers used to read cache monitoring counters (e.g. LLC occupancy) for an RMD. Parse each CMRC sub-table, ioremap its register window, and save a copy of the CMRC table in the corresponding ERDT domain entry so that later monitoring code can read the counters via MMIO. Suggested-by: Tony Luck Tested-by: Hongyu Ning Reviewed-by: Thomas Gleixner Signed-off-by: Chen Yu --- arch/x86/include/asm/resctrl.h | 2 + arch/x86/kernel/cpu/resctrl/erdt.c | 57 ++++++++++++++++++++++++++ arch/x86/kernel/cpu/resctrl/internal.h | 6 ++- 3 files changed, 64 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/resctrl.h b/arch/x86/include/asm/resctrl.h index 575f8408a9e7..e60c2aea7ebd 100644 --- a/arch/x86/include/asm/resctrl.h +++ b/arch/x86/include/asm/resctrl.h @@ -49,6 +49,8 @@ DECLARE_STATIC_KEY_FALSE(rdt_enable_key); DECLARE_STATIC_KEY_FALSE(rdt_alloc_enable_key); DECLARE_STATIC_KEY_FALSE(rdt_mon_enable_key); +int erdt_get_scale(void); + static inline bool resctrl_arch_alloc_capable(void) { return rdt_alloc_capable; diff --git a/arch/x86/kernel/cpu/resctrl/erdt.c b/arch/x86/kernel/cpu/resctrl/erdt.c index 6257869d0db2..422618991927 100644 --- a/arch/x86/kernel/cpu/resctrl/erdt.c +++ b/arch/x86/kernel/cpu/resctrl/erdt.c @@ -23,6 +23,7 @@ static LIST_HEAD(domain_info_list); static bool erdt_enabled; #define ERDT_VALID_VERSION 1 +#define CMRC_SUPPORTED_INDEX_FN 1 #define RMDD_FLAG_CPU_L3_DOMAIN BIT(0) /* Bitmask of valid sub-tables found in the first RMDD, used to ensure all RMDDs match. */ @@ -33,11 +34,19 @@ static u16 first_rmdd_domain_id; static int erdt_max_rmid; +/* Scale to bytes for the monitoring counters when ERDT is enabled. */ +static int erdt_scale; + int erdt_get_max_rmid(void) { return erdt_max_rmid; } +int erdt_get_scale(void) +{ + return erdt_scale; +} + static void __iomem *erdt_ioremap(phys_addr_t base, u32 num_pages, const char *desc) { void __iomem *addr; @@ -67,6 +76,7 @@ static void erdt_iounmap_domain(struct erdt_domain_info *domain) static void cleanup_one_domain(struct erdt_domain_info *d) { erdt_iounmap_domain(d); + kfree(d->cmrc); kfree(d); } @@ -100,6 +110,43 @@ static __init int cacd_init(struct acpi_subtbl_hdr_16 *subtbl, return 0; } +static __init int cmrc_init(struct acpi_subtbl_hdr_16 *subtbl, + struct erdt_domain_info *domain_info) +{ + struct acpi_erdt_cmrc *cmrc = (struct acpi_erdt_cmrc *)subtbl; + + if (cmrc->header.length < sizeof(*cmrc)) { + pr_warn(FW_BUG "Truncated CMRC subtable\n"); + return -EIO; + } + + if (cmrc->index_fn != CMRC_SUPPORTED_INDEX_FN) { + pr_info("Unsupported CMRC index function %u\n", cmrc->index_fn); + return -EIO; + } + + if (!cmrc->clump_size) { + pr_warn(FW_BUG "CMRC clump_size is zero\n"); + return -EIO; + } + + domain_info->base[ERDT_MMIO_CMRC_BASE] = + erdt_ioremap(cmrc->cmt_reg_base, cmrc->cmt_reg_size, "CMRC base"); + if (!domain_info->base[ERDT_MMIO_CMRC_BASE]) + return -EIO; + + domain_info->cmrc = kmemdup(cmrc, cmrc->header.length, GFP_KERNEL); + if (!domain_info->cmrc) { + iounmap(domain_info->base[ERDT_MMIO_CMRC_BASE]); + domain_info->base[ERDT_MMIO_CMRC_BASE] = NULL; + return -ENOMEM; + } + + erdt_scale = max_t(int, erdt_scale, cmrc->up_scale); + + return 0; +} + static inline struct acpi_subtbl_hdr_16 *rmdd_subtbl(struct acpi_erdt_rmdd *rmdd) { return (void *)rmdd + sizeof(*rmdd); @@ -166,6 +213,16 @@ static __init bool parse_rmdd_table(struct acpi_subtbl_hdr_16 *rmdd_hdr) goto cleanup; subtbl_mask |= BIT(ACPI_ERDT_TYPE_CACD); + break; + case ACPI_ERDT_TYPE_CMRC: + /* + * Only one CMRC is supported per domain as there is no + * method to distinguish different CMRCs within a domain. + */ + if (!(subtbl_mask & BIT(ACPI_ERDT_TYPE_CMRC)) && + !cmrc_init(subtbl, domain_info)) + subtbl_mask |= BIT(ACPI_ERDT_TYPE_CMRC); + break; default: break; diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h index d6e82eb570a3..4779f54b0c84 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -24,10 +24,12 @@ /* * Index into erdt_domain_info::base[] for each MMIO region. * @ERDT_MMIO_RMDD_CREG: RMDD control register base address + * @ERDT_MMIO_CMRC_BASE: CMRC monitoring register base address */ enum erdt_mmio_type { ERDT_MMIO_RMDD_CREG, - ERDT_MMIO_LAST = ERDT_MMIO_RMDD_CREG + ERDT_MMIO_CMRC_BASE, + ERDT_MMIO_LAST = ERDT_MMIO_CMRC_BASE }; #define ERDT_MMIO_NUM_TYPES (ERDT_MMIO_LAST + 1) @@ -35,6 +37,7 @@ enum erdt_mmio_type { /** * struct erdt_domain_info - Per-domain ERDT information * @base: Array of ioremapped MMIO region base addresses, indexed by ERDT_MMIO_* type + * @cmrc: Copy of the ACPI CMRC sub-table for this domain * @cpu_mask: CPUs belonging to this resource management domain * @max_rmid: Maximum RMID supported by this domain * @dom_id: L3 cache ID shared by all CPUs in this domain (-1 if unset) @@ -42,6 +45,7 @@ enum erdt_mmio_type { */ struct erdt_domain_info { void __iomem *base[ERDT_MMIO_NUM_TYPES]; + struct acpi_erdt_cmrc *cmrc; struct cpumask cpu_mask; u32 max_rmid; int dom_id; -- 2.43.0