From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752466AbdHGHjq (ORCPT ); Mon, 7 Aug 2017 03:39:46 -0400 Received: from mail-wm0-f66.google.com ([74.125.82.66]:36819 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752434AbdHGHjl (ORCPT ); Mon, 7 Aug 2017 03:39:41 -0400 From: Michal Simek To: linux-kernel@vger.kernel.org, monstr@monstr.eu Cc: Naga Sureshkumar Relli , =?UTF-8?q?S=C3=B6ren=20Brinkmann?= , Mauro Carvalho Chehab , Borislav Petkov , linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org Subject: [PATCH v2 6/6] edac: synopsys: Enable CE and UE interrupts for ZynqMP DDRC Date: Mon, 7 Aug 2017 09:39:28 +0200 Message-Id: <01ba1fac5b05242546c4d97dbe9a2800c1019cd8.1502091561.git.michal.simek@xilinx.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <91fd6532076e4c905b5a228d852bba4941c54a28.1502091561.git.michal.simek@xilinx.com> References: <91fd6532076e4c905b5a228d852bba4941c54a28.1502091561.git.michal.simek@xilinx.com> In-Reply-To: <91fd6532076e4c905b5a228d852bba4941c54a28.1502091561.git.michal.simek@xilinx.com> References: <91fd6532076e4c905b5a228d852bba4941c54a28.1502091561.git.michal.simek@xilinx.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Naga Sureshkumar Relli This patch enables Corrected and Uncorrected Error interrupts for ZynqMP DDRC controller Signed-off-by: Naga Sureshkumar Relli Reviewed-by: Punnaiah Choudary Kalluri Signed-off-by: Michal Simek --- Changes in v2: - Fix function alignment - Fix macro indentation drivers/edac/synopsys_edac.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index 24490334a4f2..f185a28d2db3 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -165,6 +165,8 @@ #define DDR_QOSUE_MASK 0x4 #define DDR_QOSCE_MASK 0x2 #define ECC_CE_UE_INTR_MASK 0x6 +#define DDR_QOS_IRQ_EN_OFST 0x20208 +#define DDR_QOS_IRQ_DB_OFST 0x2020C /* ECC Corrected Error Register Mask and Shifts*/ #define ECC_CEADDR0_RW_MASK 0x3FFFF @@ -1112,6 +1114,10 @@ static int synps_edac_mc_probe(struct platform_device *pdev) edac_printk(KERN_ERR, EDAC_MC, "Failed to request Irq\n"); goto free_edac_mc; } + + /* Enable UE/CE Interrupts */ + writel((DDR_QOSUE_MASK | DDR_QOSCE_MASK), + priv->baseaddr + DDR_QOS_IRQ_EN_OFST); } rc = edac_mc_add_mc(mci); @@ -1154,6 +1160,10 @@ static int synps_edac_mc_remove(struct platform_device *pdev) struct synps_edac_priv *priv; priv = mci->pvt_info; + if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) + /* Disable UE/CE Interrupts */ + writel((DDR_QOSUE_MASK | DDR_QOSCE_MASK), + priv->baseaddr + DDR_QOS_IRQ_DB_OFST); edac_mc_del_mc(&pdev->dev); if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT) synps_edac_remove_sysfs_attributes(mci); -- 1.9.1