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Mon, 9 Nov 2026 13:25:04 +0100 Received: from STKDAG1NODE1.st.com ([fe80::c1fc:16d5:3d71:a411]) by STKDAG1NODE1.st.com ([fe80::c1fc:16d5:3d71:a411%17]) with mapi id 15.02.2562.056; Mon, 9 Nov 2026 13:25:04 +0100 From: Yannick FERTRE - foss To: Dario Binacchi , "Alexandre TORGUE - foss" , Stephen Boyd CC: Marek Vasut , Gabriel FERNANDEZ - foss , "michael@amarulasolutions.com" , "linux-amarula@amarulasolutions.com" , Raphael GALLAIS-POU - foss , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-stm32@st-md-mailman.stormreply.com" Subject: Re: [RFC PATCH 4/4] arm64: dts: st: select the Engicam RMM display pixel clock source Thread-Topic: [RFC PATCH 4/4] arm64: dts: st: select the Engicam RMM display pixel clock source Thread-Index: AQHdZuSRJUR6livE9EOmCi/YZjZNOLchQTgA Date: Mon, 9 Nov 2026 12:25:04 +0000 Message-ID: <01bd9e22-b357-4093-82f7-485698be30a4@foss.st.com> References: <20261028135915.2665857-1-dario.binacchi@amarulasolutions.com> <20261028135915.2665857-5-dario.binacchi@amarulasolutions.com> In-Reply-To: <20261028135915.2665857-5-dario.binacchi@amarulasolutions.com> Accept-Language: fr-FR, en-US Content-Language: fr-FR X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-imapappendstamp: STKDAG1NODE1.st.com (15.02.2562.046) Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: DrE7N8bYd2vHAoY0SrVk7X7porbkrsNHrMWQod6TsPnRIMFaMYHg58m04LWAB6e5tzTxVp/CuaEyNc8DfvHwFn9C/h0IjF9VK0Roh2EqGJRxJVCuV6679xOUDXI9zGf/W066CAIU+bq2RtByivOLg93Qw3nNT6uO1EDUwzH4sD2HUrxojcEyKHXIXFnEXm4ZY4bEQbHcejc3odeG7ONAU9GkfH8qhnt5jkJqCj310c0S2QaMygUzQoSAk02dn3JaGiZ2WI36IlBWJmWz14mNAujb3/MIMOSbnNOquN/YamLHg4EkhO+siABhMJpAaLB8mHVl6EoXlTxNlvlkpmqh1xCCk6CbNYV0G7ELz3EH3IswKHOY7suJI1w3rlmdov4Iv8bsp8B0ZPpA358m4ttu1bOs7QADrNBI35S7zR1v0A8W5NnQhmYtGmDGNfZQ80ze X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2026 12:25:05.7022 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 98439c1a-1fc8-4a25-7b5e-08df3e5c7c97 X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.59];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: DB3PEPF00008859.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR10MB7105 Hi Dario, The parent clock of ltdc must not be assigned in the DTS file. The ltdc driver must check the display path at probe=A0 and assign the=20 parent clock based on the type of connected panel (LVDS/DSI or DPI). Best regards On 10/28/26 14:59, Dario Binacchi wrote: > On STM32MP255/257 the LTDC pixel clock is selected by the SYSCFG > pixel clock mux, whose reset value is the LVDS PHY pixel clock. With > the RGB panel the LTDC is then clocked by the unused LVDS PHY, and every > commit times out: > > [CRTC:42:crtc-0] vblank wait timed out > [drm] *ERROR* flip_done timed out > > Select the LTDC kernel clock as pixel clock source in the RGB panel > overlay and, for consistency, without relying on the reset value, the > LVDS PHY pixel clock in the LVDS panel overlay. > > Signed-off-by: Dario Binacchi > > --- > > ...57d-engicam-microgea-rmm-overlay-am-1280800w8tzqw-t00h.dtso | 3 +++ > ...2mp257d-engicam-microgea-rmm-overlay-rk050hr345-ct106a.dtso | 2 ++ > 2 files changed, 5 insertions(+) > > diff --git a/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm-over= lay-am-1280800w8tzqw-t00h.dtso b/arch/arm64/boot/dts/st/stm32mp257d-engicam= -microgea-rmm-overlay-am-1280800w8tzqw-t00h.dtso > index 7655c1bf56b1..b44e1d3ddb1b 100644 > --- a/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm-overlay-am-= 1280800w8tzqw-t00h.dtso > +++ b/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm-overlay-am-= 1280800w8tzqw-t00h.dtso > @@ -32,6 +32,9 @@ &framebuffer { > }; > =20 > <dc { > + /* LVDS output: the pixel clock is the LVDS PHY one */ > + assigned-clocks =3D <&syscfg>; > + assigned-clock-parents =3D <&lvds>; > status =3D "okay"; > =20 > port { > diff --git a/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm-over= lay-rk050hr345-ct106a.dtso b/arch/arm64/boot/dts/st/stm32mp257d-engicam-mic= rogea-rmm-overlay-rk050hr345-ct106a.dtso > index 7be955be58ed..7855086c33c7 100644 > --- a/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm-overlay-rk0= 50hr345-ct106a.dtso > +++ b/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm-overlay-rk0= 50hr345-ct106a.dtso > @@ -38,6 +38,8 @@ touchscreen@38 { > <dc { > /* RGB output: the pixel clock is the LTDC kernel clock */ > clocks =3D <&rcc CK_KER_LTDC>, <&rcc CK_BUS_LTDC>, <&syscfg>, <&lvds>; > + assigned-clocks =3D <&syscfg>; > + assigned-clock-parents =3D <&rcc CK_KER_LTDC>; > pinctrl-names =3D "default", "sleep"; > pinctrl-0 =3D <<dc_pins_a>; > pinctrl-1 =3D <<dc_sleep_pins_a>;