From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F815331ED6 for ; Sun, 2 Aug 2026 16:15:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785687302; cv=none; b=AraKKzjsBTac/T/vkMXOQ69ZspISck6r+04QDx64M45/8IRnk2VuwcMXmTn5QR+aF+D2PkPQU9YRchC7fSQc1GnKOsYCkkC/6JSQMW8oVumu21C0c34F7CpremFj+hm0ChwFfu49DMc5ehMT2usYJzuNGuB9BmVF4QRuNb0EkK8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785687302; c=relaxed/simple; bh=20b3XueljqzzBYEWHLJjPuf4rSox4zGXnDETXiKH4Co=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fW2ZFosAdeqqSTSJ6UTepmdPJOA+sjvwpzDWXsw9FUXR32GQ97gwfHj491F5c7tSm/P/EnKICJXLE4n8T11xzwSRMFj4wp99sihElR4jZ3JC7VOyn/t63ZSqITGUuK9LjMHxkDwbmMNdqd4YnXQLwsFSrTacOe2kvhkOg92xOQA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Rl8ZrBgQ; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Rl8ZrBgQ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1785687300; x=1817223300; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=20b3XueljqzzBYEWHLJjPuf4rSox4zGXnDETXiKH4Co=; b=Rl8ZrBgQ9JJDzGYFS/3lnesV7BOUd0KUS3wZYqhOqqh+W8wuPVmFoaWq aiCgVHNVZGfMEN6nd5n63wm6kWRXwsTuyjHUW178VIZVHmYKhd/VYoBwm WAKXk18i09/ltfs0u4e4aq5bUGw0jeVTw9anCxlNe8RqtohmOaxlJFm8v hXjco8XXTSLzTtNOESdQ+0W8H+9jw7wj+WdcZf42z6RxaeywMAZ1FifWI VoKttg1IyULNo8aYxdRxTWJ/MnDis6YDSQzuWLA2P2ISVOLblUiPOajFG QlDIpKs4fVctrTcEjLtCEv3yHcb34JxKukQ2sTxWEB/Y+MSIKSiVyL3ZO g==; X-CSE-ConnectionGUID: Z7Lvaw74RLKNj7hRUUKMlA== X-CSE-MsgGUID: RVJY3EH4Q9yYBqUKdzlg9w== X-IronPort-AV: E=McAfee;i="6800,10657,11863"; a="89915476" X-IronPort-AV: E=Sophos;i="6.25,200,1779174000"; d="scan'208";a="89915476" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Aug 2026 09:15:00 -0700 X-CSE-ConnectionGUID: ToCaz8DES5emLLgxWXjOhA== X-CSE-MsgGUID: TquWo/ZOT6yq1M77ddpUlA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,200,1779174000"; d="scan'208";a="261622071" Received: from chenyu-dev.sh.intel.com ([10.239.62.107]) by orviesa009.jf.intel.com with ESMTP; 02 Aug 2026 09:14:57 -0700 From: Chen Yu To: Reinette Chatre , Tony Luck Cc: Ben Horgan , "James Morse" , Dave Martin , Babu Moger , Fenghua Yu , Borislav Petkov , Thomas Gleixner , "Dave Hansen" , Peter Newman , chen.yu@linux.dev, x86@kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 09/31] x86/resctrl: Add MMIO-based LLC occupancy monitoring support Date: Mon, 3 Aug 2026 00:05:15 +0800 Message-Id: <01e5f9d1e4f04c6e327fe2a9865f5c9ea9e97dbe.1785680802.git.yu.c.chen@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add erdt_mon_read() to read LLC occupancy via MMIO and use it when the platform supports ERDT. Register the L3 occupancy event with ERDT enabled when available, falling back to the MSR-based path otherwise. Use the CMRC (Cache Monitoring Registers for CPU Agents Description) ACPI sub-table to read LLC occupancy counters for each RMID via MMIO when ERDT is enabled. This CMRC information is stored in the rdt_hw_l3_mon_domain, which could be accessed directly. Currently, the per-domain limbo handler is still in use. There is no need to switch to a global limbo handler, because even after such a switch, the worker thread would still have to iterate through all domains one by one. The per-domain handler already accomplishes this using a worker thread rather than costly IPIs, so there is no clear benefit to switching to a global handler. Suggested-by: Reinette Chatre Tested-by: Hongyu Ning Signed-off-by: Chen Yu --- arch/x86/include/asm/resctrl.h | 8 +++- arch/x86/kernel/cpu/resctrl/core.c | 5 ++- arch/x86/kernel/cpu/resctrl/erdt.c | 59 ++++++++++++++++++++++++++ arch/x86/kernel/cpu/resctrl/internal.h | 7 ++- arch/x86/kernel/cpu/resctrl/monitor.c | 9 +++- 5 files changed, 84 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/resctrl.h b/arch/x86/include/asm/resctrl.h index 5491853113dd..0948f64856ef 100644 --- a/arch/x86/include/asm/resctrl.h +++ b/arch/x86/include/asm/resctrl.h @@ -132,7 +132,13 @@ static inline void __resctrl_sched_in(struct task_struct *tsk) static inline unsigned int resctrl_arch_round_mon_val(unsigned int val) { - unsigned int scale = boot_cpu_data.x86_cache_occ_scale; + unsigned int scale = boot_cpu_data.x86_cache_occ_scale, escale; + + if (erdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC)) { + escale = erdt_get_scale(); + if (escale) + scale = escale; + } /* h/w works in units of "boot_cpu_data.x86_cache_occ_scale" */ val /= scale; diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c index 5a56966103f2..07d669e6e11b 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -1131,7 +1131,10 @@ static __init bool get_rdt_mon_resources(void) struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; bool ret = false; - if (rdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC)) { + if (erdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC)) { + resctrl_enable_mon_event(QOS_L3_OCCUP_EVENT_ID, true, 0, NULL); + ret = true; + } else if (rdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC)) { resctrl_enable_mon_event(QOS_L3_OCCUP_EVENT_ID, false, 0, NULL); ret = true; } diff --git a/arch/x86/kernel/cpu/resctrl/erdt.c b/arch/x86/kernel/cpu/resctrl/erdt.c index 167d2dfc368d..5f9377c80be6 100644 --- a/arch/x86/kernel/cpu/resctrl/erdt.c +++ b/arch/x86/kernel/cpu/resctrl/erdt.c @@ -26,6 +26,10 @@ static bool erdt_enabled; #define CMRC_SUPPORTED_INDEX_FN 1 #define RMDD_FLAG_CPU_L3_DOMAIN BIT(0) +/* Set in a monitoring counter when it holds no valid data to report. */ +#define UNAVAILABLE_COUNTER BIT_ULL(63) +#define CMRC_FLAG_UNAVAILABLE_BIT BIT(0) + /* Bitmask of valid sub-tables found in the first RMDD, used to ensure all RMDDs match. */ static u32 valid_subtbl_mask; @@ -39,6 +43,9 @@ static int erdt_scale; bool erdt_support(int flag) { + if (flag == X86_FEATURE_CQM_OCCUP_LLC) + return valid_subtbl_mask & BIT(ACPI_ERDT_TYPE_CMRC); + return false; } @@ -52,6 +59,58 @@ int erdt_get_scale(void) return erdt_scale; } +static u32 cmrc_index_function_1(struct acpi_erdt_cmrc *cmrc, u32 rmid) +{ + /* + * MMIO_offset_for_RMID# = + * (RMID / ClumpSize) * Stride + + * (RMID % ClumpSize) * 8 + */ + return (rmid / cmrc->clump_size) * cmrc->clump_stride + + (rmid % cmrc->clump_size) * 8; +} + +static int erdt_read_l3_occupancy(const struct erdt_domain_info *d, u32 rmid, u64 *val) +{ + struct acpi_erdt_cmrc *cmrc; + u64 l3_cmt_count; + u32 offset; + + cmrc = d->cmrc; + if (!cmrc) + return -EIO; + + offset = cmrc_index_function_1(cmrc, rmid); + /* Overflow of cmt_reg_size * SZ_4K already validated in erdt_ioremap(). */ + if (offset + sizeof(u64) > (u32)cmrc->cmt_reg_size * SZ_4K) + return -EINVAL; + + l3_cmt_count = readq(d->base[ERDT_MMIO_CMRC_BASE] + offset); + if ((cmrc->flags & CMRC_FLAG_UNAVAILABLE_BIT) && + (l3_cmt_count & UNAVAILABLE_COUNTER)) + return -EINVAL; + + *val = l3_cmt_count * cmrc->up_scale; + + return 0; +} + +int erdt_mon_read(struct rdt_domain_hdr *hdr, enum resctrl_event_id evtid, u32 rmid, u64 *val) +{ + struct rdt_hw_l3_mon_domain *hw_dom; + const struct erdt_domain_info *d; + + hw_dom = resctrl_to_arch_mon_dom(container_of(hdr, struct rdt_l3_mon_domain, hdr)); + d = hw_dom->d_info; + if (!d) + return -EIO; + + if (evtid == QOS_L3_OCCUP_EVENT_ID) + return erdt_read_l3_occupancy(d, rmid, val); + + return -EIO; +} + static void __iomem *erdt_ioremap(phys_addr_t base, u32 num_pages, const char *desc) { void __iomem *addr; diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h index ee1990302177..c175d8884516 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -175,7 +175,11 @@ struct rdt_perf_pkg_mon_domain { * resctrl_arch_get_num_closid() to avoid confusion * with struct rdt_resource_final's property of the same * name, which has been corrected for features like CDP. - * @mon_scale: cqm counter * mon_scale = occupancy in bytes + * @mon_scale: Scale factor applied to a raw counter value on the + * MSR-based read path: CMT occupancy counter * mon_scale = + * occupancy in bytes, and MBM chunk count * mon_scale = bytes + * transferred. ERDT reads occupancy via MMIO and applies its + * own firmware-provided scale instead. * @mbm_width: Monitor width, to detect and correct for overflow. * @cdp_enabled: CDP state of this resource * @has_per_cpu_cache_cfg: True if QOS_CFG register for this cache resource @@ -308,6 +312,7 @@ static inline bool intel_handle_aet_option(bool force_off, char *tok) { return f bool erdt_support(int flag); bool erdt_cpu_has(int flag); int erdt_get_max_rmid(void); +int erdt_mon_read(struct rdt_domain_hdr *hdr, enum resctrl_event_id evtid, u32 rmid, u64 *val); int erdt_init(void); void erdt_exit(void); diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c index 30ff6b0293ab..0e011b1f7fd2 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -278,6 +278,10 @@ int resctrl_arch_rmid_read(struct rdt_resource *r, struct rdt_domain_hdr *hdr, switch (r->rid) { case RDT_RESOURCE_L3: + if (eventid == QOS_L3_OCCUP_EVENT_ID && + erdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC)) + return erdt_mon_read(hdr, eventid, rmid, val); + return arch_l3_read_event(hdr, rmid, eventid, val, r); case RDT_RESOURCE_PERF_PKG: return intel_aet_read_event(hdr->id, rmid, arch_priv, val); @@ -419,12 +423,15 @@ int __init rdt_get_l3_mon_config(struct rdt_resource *r) struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); unsigned int threshold; u32 eax, ebx, ecx, edx; + int max_rmid; snc_nodes_per_l3_cache = snc_get_config(); + max_rmid = erdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC) ? + erdt_get_max_rmid() : boot_cpu_data.x86_cache_max_rmid; resctrl_rmid_realloc_limit = boot_cpu_data.x86_cache_size * 1024; hw_res->mon_scale = boot_cpu_data.x86_cache_occ_scale / snc_nodes_per_l3_cache; - r->mon.num_rmid = (boot_cpu_data.x86_cache_max_rmid + 1) / snc_nodes_per_l3_cache; + r->mon.num_rmid = (max_rmid + 1) / snc_nodes_per_l3_cache; hw_res->mbm_width = MBM_CNTR_WIDTH_BASE; if (mbm_offset > 0 && mbm_offset <= MBM_CNTR_WIDTH_OFFSET_MAX) -- 2.43.0