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Thu, 4 Jul 2024 23:19:30 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.11.0-alpha0-566-g3812ddbbc-fm-20240627.001-g3812ddbb Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <01eb9efd-ca7a-4d4c-a29d-cfc2f6cfbb86@app.fastmail.com> In-Reply-To: <554b10e8-a7ab-424a-f987-ea679859a220@loongson.cn> References: <20240626063239.3722175-1-maobibo@loongson.cn> <20240626063239.3722175-3-maobibo@loongson.cn> <79dcf093-614f-2737-bb03-698b0b3abc57@loongson.cn> <9c7d242e-660b-8d39-b69e-201fd0a4bfbf@loongson.cn> <059d66e4-dd5d-0091-01d9-11aaba9297bd@loongson.cn> <7e6a1dbc-779a-4669-4541-c5952c9bdf24@loongson.cn> <81dded06-ad03-9aed-3f07-cf19c5538723@loongson.cn> <0e28596c-3fe9-b716-b193-200b9b1d5516@loongson.cn> <554b10e8-a7ab-424a-f987-ea679859a220@loongson.cn> Date: Fri, 05 Jul 2024 11:19:09 +0800 From: "Jiaxun Yang" To: "Bibo Mao" , "Huacai Chen" Cc: "Tianrui Zhao" , "Xuerui Wang" , kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 2/3] LoongArch: KVM: Add LBT feature detection function Content-Type: text/plain;charset=utf-8 Content-Transfer-Encoding: quoted-printable =E5=9C=A82024=E5=B9=B47=E6=9C=885=E6=97=A5=E4=B8=83=E6=9C=88 =E4=B8=8A=E5= =8D=889:21=EF=BC=8Cmaobibo=E5=86=99=E9=81=93=EF=BC=9A [...] >> for you. > On the other hand, can you list benefits or disadvantage of approaches=20 > on different architecture? So the obvious benefit of scratch vCPU would be maintaining consistency = and simpleness for UAPI. It can also maximum code reuse probabilities in other user space hypervi= sor projects. Also, it can benefit a potential asymmetrical system. I understand that = it won't appear in near future, but we should always be prepared, especially in UAPI des= ign. > > Or you post patch about host cpu support, I list its disadvantage. Or = I=20 > post patch about host cpu support with scheduled time, then we talk=20 > about it. Is that fair for you? I'm not committed to development work, I can try, but I can't promise. Regarding the fairness, IMO that's not how community works. If you obser= ve reviewing process happening all the place, it's always about addressing other's co= ncern. Still, it's up to maintainers to decide what's reasonable, I'm just tryi= ng to help. > > It is unfair that you list some approaches and let others spend time t= o=20 > do, else you are my top boss :) I mean, I'm just trying to make some progress here. I saw you have some = disagreement with Huacai. I know QEMU side implementation better than Huacai, so I'm trying to pro= pose a solution that would address Huacai's concern and may work for you. >>=20 >> I understand you may have some plans in your mind, please elaborate s= o=20 >> we can smash >> them together. That's how community work. >>=20 >>> >>> For host cpu type or migration feature detection, I have no idea now= ,=20 >>> also I do not think it will be big issue for me, I will do it with=20 >>> scheduled time. Of source, welcome Jiaxun and you to implement host=20 >>> cpu type or migration feature detection. >>=20 >> My concern is if you allow CPU features to have "auto" property you a= re=20 >> risking create >> inconsistency among migration.=C2=A0Once you've done that it's pretty= hard to=20 >> get rid of it. >>=20 >> Please check how RISC-V dealing with CPU features at QMP side.We are = working on >>=20 >> I'm not meant to hinder your development work, but we should always=20 >> think ahead. > Yes, it is potential issue and we will solve it. Another potential iss= ue=20 > is that PV features may different on host, you cannot disable PV=20 > features directly. The best way is that you post patch about it, then=20 > we can talk about together, else it may be kindly reminder, also may b= e=20 > waste of time, everyone is busy working for boss :) Sigh, so you meant you submitted something known to be problematic? --=20 - Jiaxun