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Fri, 03 Apr 2026 03:17:40 -0700 (PDT) Message-ID: <01ffe5d3aca040edcedb084386ab6e195cb93013.camel@linaro.org> Subject: Re: [PATCH v2 2/7] dt-bindings: soc: samsung: exynos-pmu: add samsung,pmu-intr-gen phandle From: =?ISO-8859-1?Q?Andr=E9?= Draszik To: Alexey Klimov , Sam Protsenko , linux-samsung-soc@vger.kernel.org, Krzysztof Kozlowski , Peter Griffin , Conor Dooley , Alim Akhtar Cc: Tudor Ambarus , Rob Herring , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Date: Fri, 03 Apr 2026 11:17:47 +0100 In-Reply-To: <20260401-exynos850-cpuhotplug-v2-2-c5a760a3e259@linaro.org> References: <20260401-exynos850-cpuhotplug-v2-0-c5a760a3e259@linaro.org> <20260401-exynos850-cpuhotplug-v2-2-c5a760a3e259@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2-8+build1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Hi Alexey, On Wed, 2026-04-01 at 05:51 +0100, Alexey Klimov wrote: > Some Exynos-based SoCs, for instance Exynos850, require access > to the pmu interrupt generation register region which is exposed > as a syscon. Update the exynos-pmu bindings documentation to > reflect this. You could mention that this is similar to the existing google,... one due to same requirement, hence a new and more general property. >=20 > Signed-off-by: Alexey Klimov > --- > =C2=A0.../devicetree/bindings/soc/samsung/exynos-pmu.yaml=C2=A0=C2=A0=C2= =A0 | 18 ++++++++++++++++++ > =C2=A01 file changed, 18 insertions(+) >=20 > diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yam= l b/Documentation/devicetree/bindings/soc/samsung/exynos- > pmu.yaml > index 76ce7e98c10f..92acdfd5d44e 100644 > --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml > +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml > @@ -110,6 +110,11 @@ properties: > =C2=A0=C2=A0=C2=A0=C2=A0 description: > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 Node for reboot method > =C2=A0 > +=C2=A0 samsung,pmu-intr-gen-syscon: > +=C2=A0=C2=A0=C2=A0 $ref: /schemas/types.yaml#/definitions/phandle > +=C2=A0=C2=A0=C2=A0 description: > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 Phandle to PMU interrupt generation inter= face. > + > =C2=A0=C2=A0 google,pmu-intr-gen-syscon: Please keep alphabetical order of vendors. Cheers, Andre'