From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934233AbeAXPNR (ORCPT ); Wed, 24 Jan 2018 10:13:17 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:38901 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934032AbeAXPNN (ORCPT ); Wed, 24 Jan 2018 10:13:13 -0500 X-Google-Smtp-Source: AH8x224YgssQqb/iEpB/l5p1YGoGY36XT7RWv0ONjXCCDRO8+U+JWSZwnLbeIVp8lD4uQgU4Qa8hWg== Subject: Re: [PATCH 2/3] arm64: dts: mt6797: add pwrap support for mt6797 To: argus.lin@mediatek.com, Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon Cc: Chenglin Xu , Sean Wang , wsd_upstream@mediatek.com, henryc.chen@mediatek.com, flora.fu@mediatek.com, Chen Zhong , Christophe Jaillet , "shailendra . v" , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org References: <20180123033659.11401-1-argus.lin@mediatek.com> <20180123033659.11401-2-argus.lin@mediatek.com> From: Matthias Brugger Message-ID: <02292414-1f47-8614-df89-3e5653aecc70@gmail.com> Date: Wed, 24 Jan 2018 16:13:10 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.4.0 MIME-Version: 1.0 In-Reply-To: <20180123033659.11401-2-argus.lin@mediatek.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 01/23/2018 04:36 AM, argus.lin@mediatek.com wrote: > From: Argus Lin > > mt6797 is a highly integrated SoCs, and it uses > mt6351 as Power Management IC. > We need to add pwrap device to communicate with > mt6351 by SPI. > The base address of pwrap is 0x1000d000, and IRQ > number is 178. It also using fixed 26Mhz clock > as SPI CLK. > > Change-Id: I07a8b794a019c2a980bb1f974defeff4e7df5693 No Change-Ids please :)