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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8942e6040casm19565916d6.21.2026.01.16.00.34.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 16 Jan 2026 00:34:25 -0800 (PST) Message-ID: <025cefd3-888b-4744-bde3-2d5c007db66f@oss.qualcomm.com> Date: Fri, 16 Jan 2026 16:34:16 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/5] dt-bindings: i2c: qcom-cci: Document sm6150 compatible To: Krzysztof Kozlowski Cc: Loic Poulain , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org References: <20260115-sm6150_evk-v3-0-81526dd15543@oss.qualcomm.com> <20260115-sm6150_evk-v3-2-81526dd15543@oss.qualcomm.com> <20260116-malachite-spaniel-of-refinement-af22ae@quoll> Content-Language: en-US From: Wenmeng Liu In-Reply-To: <20260116-malachite-spaniel-of-refinement-af22ae@quoll> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: qYuTIJDwV3KrfR7MSXvkcUcCD0b51g8a X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTE2MDA2MSBTYWx0ZWRfX7qc4OWv0HdtI Am7Pxiudt0eIzB0Pv8QZj4+I0GljIWiYBcISZImqnfbS/I9minjfoQDsBisvNNE1YkH1CzATgIk fYbPCAen2/Rf0plv58s8LmIMHrFBn0zfMf0BK0W+mlVaYSkduCC+AnuDD4nb4CwmmGBceDt53O3 V4ff40S7InckJgBdAqRCdCBSm+QJD9elcjmIcVANJsC/plPFbbRzVNt/lWd6S1G+jKPNR8gyNOX +negCF3szyIyYvHdQMt3Ld3tdWbr71ttwvh6ZhEKd7AHfzTjYs9lcp4J9saUosm9XLEktLD3a4g 02Pu6AdhTPNS4vZdWS6SlGapvGOFOPtxUrnWWQvozbJ6CA8uRdlr8RALZV/mbTeKKyO6AdHGwW5 XNkFX7Ko+8n2OpdPG3UJcDlC/uAKxRyA80KD5KdqpbjRWOBMJhaKr9f2U7oPKbRFh/hfG0q05Hd zJ90NIMywzPGBRM7EkA== X-Proofpoint-GUID: qYuTIJDwV3KrfR7MSXvkcUcCD0b51g8a X-Authority-Analysis: v=2.4 cv=M9tA6iws c=1 sm=1 tr=0 ts=6969f814 cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=-6nChnoGJk84s89d4NQA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=iYH6xdkBrDN1Jqds4HTS:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-16_02,2026-01-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 malwarescore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 adultscore=0 spamscore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601160061 On 1/16/2026 4:28 PM, Krzysztof Kozlowski wrote: > On Thu, Jan 15, 2026 at 06:12:38PM +0800, Wenmeng Liu wrote: >> Add the sm6150 CCI device string compatible. >> >> SM6150 include three clock: >> bus: Bus clock responsible for data transfer. >> iface: Interface clock responsible for register read and write. >> cci: Clock for CCI core operations. >> >> Signed-off-by: Wenmeng Liu >> Reviewed-by: Vladimir Zapolskiy >> --- >> .../devicetree/bindings/i2c/qcom,i2c-cci.yaml | 18 ++++++++++++++++++ >> 1 file changed, 18 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml >> index a3fe1eea6aece9685674feaa5ec53765c1ce23d8..3472670fdc908ef8f3b3afc68ff437c0435b69a7 100644 >> --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml >> +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml >> @@ -33,6 +33,7 @@ properties: >> - qcom,sc8280xp-cci >> - qcom,sdm670-cci >> - qcom,sdm845-cci >> + - qcom,sm6150-cci >> - qcom,sm6350-cci >> - qcom,sm8250-cci >> - qcom,sm8450-cci >> @@ -263,6 +264,23 @@ allOf: >> - const: cpas_ahb >> - const: cci >> >> + - if: >> + properties: >> + compatible: >> + contains: >> + enum: >> + - qcom,sm6150-cci >> + then: >> + properties: >> + clocks: >> + minItems: 3 >> + maxItems: 3 >> + clock-names: >> + items: >> + - const: bus >> + - const: iface >> + - const: cci > > So basically the same as camnoc_axi+cpas_ahb+cci, so just put it into > existing enum with qcom,sm8550-cci. > > I asked for this at v1. > https://lore.kernel.org/all/43efa6fd-53c3-4680-8aca-7b37089ca295@kernel.org/ > > > Best regards, > Krzysztof > I raised this question in the previous version. And got reply as: --- me: + clocks = <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cci"; clocks = <&camcc CAM_CC_SOC_AHB_CLK>, clock-names = "camnoc_axi"; If this is acceptable, I will update it this way in the next version. --- Loic: No, the idea is to name the clock from the device’s perspective. For example, from the CCI perspective, you typically have: - A core clock, clocking the logic, which could be named 'core' (but 'cci' here is ok) - Clocks related to the bus interfaces (such as AHB or AXI), which could be named 'iface...' or 'bus...'. This approach clearly identifies the role of each clock and keeps naming consistent, without depending on where the clock originates or its source name. From that standpoint, some of the existing bus clock names defined in qcom,i2c-cci.yaml are not ideal. You can find better naming in bindings like qcom,i2c-qup.yaml or qcom,i2c-geni-qcom.yaml. --- clocks = <&camcc CAM_CC_SOC_AHB_CLK>, clock-names = "camnoc_axi"; so is this acceptable? Thanks, Wenmeng