From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751601AbcEMHrq (ORCPT ); Fri, 13 May 2016 03:47:46 -0400 Received: from lucky1.263xmail.com ([211.157.147.132]:54265 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750889AbcEMHrp (ORCPT ); Fri, 13 May 2016 03:47:45 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-RL-SENDER: shawn.lin@rock-chips.com X-FST-TO: linux-arm-kernel@lists.infradead.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: shawn.lin@rock-chips.com X-UNIQUE-TAG: <75afd1c982c7d6e5c821df1dec44d600> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Subject: Re: [PATCH 2/2] clk: rockchip: fix the rk3399 sdmmc sample shift To: Doug Anderson References: <1463076197-15900-1-git-send-email-dianders@chromium.org> <1463076197-15900-2-git-send-email-dianders@chromium.org> <20160512231023.GA63308@google.com> <84673e7c-dd64-b2ca-5c7c-5c7f34d239d8@rock-chips.com> Cc: shawn.lin@rock-chips.com, Brian Norris , Heiko Stuebner , Michael Turquette , Stephen Boyd , Xing Zheng , "linux-kernel@vger.kernel.org" , "open list:ARM/Rockchip SoC..." , linux-clk , "linux-arm-kernel@lists.infradead.org" From: Shawn Lin Message-ID: <0261c4b4-7398-fe15-5e26-f92bfbe79f3c@rock-chips.com> Date: Fri, 13 May 2016 15:46:54 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.3; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 在 2016/5/13 12:36, Doug Anderson 写道: > Shawn, > > On Thu, May 12, 2016 at 4:47 PM, Shawn Lin wrote: >> 在 2016/5/13 7:10, Brian Norris 写道: >>> >>> On Thu, May 12, 2016 at 11:03:17AM -0700, Doug Anderson wrote: >>>> >>>> Just like every other Rockhip device, the MMC "_sample" clocks should >>>> have a shift of 0, not a shift of 1. The rk3399 TRM agrees. Presumably >>>> these values were set to 0 because of a typo. >>> >>> >>> I'll semi-disagree about the TRM: the TRM doesn't seem to agree with >>> itself, so it sometimes agrees with you and sometimes doesn't :) >>> >>> On page 79 of the 2nd (?) book, it looks like {SDMMC,SDIO}_CON{0,}[2:1] >>> are {drv,sample}_degree. But on page 208 of the 1st book, those are put >>> at bits [1:0]. >>> >> >> >> Please refer to Mobile Strorage Host Controller section for anything >> about sdmmc/sdio. So shift should be 1. >> >> Sometime I also get bothered to address it. Anyway, I will always keep >> a eye on it from now on..... > > I still in general have mistrust for TRM docs for things like this. > Have you verified that this was an intentional change for rk3399, or > could it be a typo? Typically SoCs don't change this type of stuff > for no reason. > Typically it doesn't, but the reality is that {SDMMC,SDIO}_CON{0,}[2:1] for drv/sample_degree both. Obviously they want to make drv stuff the same layout as sampe stuff... > This should be possible to verify in one of two ways. If the TRM has > a typo and things truly _do_ start at 0 instead of 1, then: > > 1. There will be roughly mirrors of valid ranges. > 2. Things won't match up if we change tuning to use 180 course offsets > and the rest fine offsets. > > It would be ideal if you could confirm with the chip guys, but if you I have checked it before Xing upstreamed the code, but as your question on the TRM, I check it with the chip guys again. So the answer is that drv/sample stuff should refer to Mobile Strorage Host Controller section, and it will fit the future Socs from now on. > can't I'll try to do more tests tomorrow. > > > -- Best Regards Shawn Lin