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From: Tom Lendacky <thomas.lendacky@amd.com>
To: Dave Hansen <dave.hansen@intel.com>,
	linux-kernel@vger.kernel.org, x86@kernel.org
Cc: Thomas Gleixner <tglx@kernel.org>, Ingo Molnar <mingo@redhat.com>,
	Borislav Petkov <bp@alien8.de>,
	Dave Hansen <dave.hansen@linux.intel.com>,
	"H. Peter Anvin" <hpa@zytor.com>,
	Andy Lutomirski <luto@kernel.org>,
	Peter Zijlstra <peterz@infradead.org>,
	Nadav Amit <nadav.amit@gmail.com>,
	Rik van Riel <riel@surriel.com>
Subject: Re: [PATCH] x86/mm: Skip global ASID broadcast TLB flush when PCID is disabled
Date: Thu, 14 May 2026 15:24:52 -0500	[thread overview]
Message-ID: <0276dd43-43c1-4646-b803-f24faf4fcccd@amd.com> (raw)
In-Reply-To: <c71ab05a-f02d-466b-8007-5b5c5f344249@intel.com>

On 5/13/26 13:29, Dave Hansen wrote:
> On 5/13/26 11:11, Tom Lendacky wrote:
>> Booting with "nopcid" clears X86_FEATURE_PCID in x86_nopcid_setup(),
>> but X86_FEATURE_INVLPGB is left intact. On AMD CPUs that support
>> INVLPGB, broadcast TLB flushing remains active even though CR4.PCIDE
>> is off.
>>
>> There are two checks that decide whether the global ASID code runs,
>> mm_global_asid() and consider_global_asid(), that key off of the
>> X86_FEATURE_INVLPGB feature. Once an mm becomes active on more than
>> three CPUs, consider_global_asid() assigns it a global ASID, after which
>> flush_tlb_mm_range() takes the broadcast_tlb_flush() path. The
>> broadcast_tlb_flush() function calls invlpgb_flush_single_pcid_nosync() or
>> invlpgb_flush_user_nr_nosync() with kern_pcid(asid), which expands to
>> (asid + 1).  Both helpers set INVLPGB_FLAG_PCID and place the non-zero
>> PCID into EDX[31:16] of the INVLPGB instruction. Issuing INVLPGB with
>> INVLPGB_FLAG_PCID (RAX[1]) and a non-zero PCID (RDX[27:16]) while
>> CR4.PCIDE is not set results in a #GP:
> 
> Just to be clear, the APM says there's a #GP if: "CR4.PCID =0 and
> EDX[PCID] is not zero." I don't think INVLPGB_FLAG_PCID (RAX[1]) is
> supposed to play a role.
> 
> Although the architecture doesn't care, it's also at least a _little_
> funky to be setting INVLPGB_FLAG_PCID here:
> 
>         u8 flags = INVLPGB_FLAG_PCID | INVLPGB_FLAG_VA;
> 
> when PCIDs are disabled.
> 
> How about we add a:
> 
> static const struct cpuid_dep cpuid_deps[] = {
> ...
>         { X86_FEATURE_INVLPGB,                 X86_FEATURE_PCID   },
> 
> and be done with it?
> 
> If you don't have PCIDs, you don't get INVLPGB at all. Yes, you could
> theoretically use INVLPGB for kernel mappings without PCIDs. But all
> actual CPUs that have INVLPGB presumably also have PCID support.
> 
> Then we never have to worry about cases where INVLPGB==1, but PCID==0 at
> *all*.

That's ok with me. Tested and confirmed working. I can submit a v2 if
everyone is ok with this approach. I'll give it a couple of more days...

Thanks,
Tom



      reply	other threads:[~2026-05-14 20:24 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-13 18:11 Tom Lendacky
2026-05-13 18:13 ` Tom Lendacky
2026-05-13 18:29 ` Dave Hansen
2026-05-14 20:24   ` Tom Lendacky [this message]

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