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AJvYcCUtBL5E+DwyzCWazApX1/oaK8GDXa3H5DS1VaoSfvGNC7uF3JJoHSSmTnMrH1TbRUKIyftmwFSMOIAp@vger.kernel.org, AJvYcCVb9PlnX6ZG4vDvf2O5sV9USOqmq56XH4udzDXzk1fHC8EZ8+SEvVetkivXJFI0HqXupcXtpacRDwPq@vger.kernel.org, AJvYcCWgTeF6oMqdtwg9Lfw0de8gPLnKjMmW59E2LEZu+TpqG3KQijlF/gSB2TFZ8ksrMu4YX2OeEMvzxVYl/OFa@vger.kernel.org X-Gm-Message-State: AOJu0YxXiqXJfhh9mOomx7yMs7sDk3CkOjPzKDJYgf84PWVIw9vVRzxI FObCnyN2MqMaS6x7t07Ii66E6bV98fivSAXOGaBT79WqO9ZrijYupH1sAYrh X-Google-Smtp-Source: AGHT+IEUkmo6BSFMfs3DhvYxndBIE+RTpexMHgWjQyytLnGrtanEQDgJwQ5jLMmGoecdNAvUv0gKiA== X-Received: by 2002:a05:6402:5408:b0:5c8:93fe:3f7e with SMTP id 4fb4d7f45d1cf-5c933550288mr3177019a12.11.1728565946608; Thu, 10 Oct 2024 06:12:26 -0700 (PDT) Received: from [10.31.18.55] ([95.183.227.31]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5c9370d2560sm761734a12.17.2024.10.10.06.12.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 10 Oct 2024 06:12:26 -0700 (PDT) Message-ID: <02a0487d-4538-4796-b779-da059f4e6ddd@gmail.com> Date: Thu, 10 Oct 2024 16:12:20 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 2/2] clk: mediatek: Add drivers for MediaTek MT6735 main clock and reset drivers To: AngeloGioacchino Del Regno , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , Philipp Zabel , Sam Shih , Daniel Golle , Bartosz Golaszewski Cc: Yassine Oudjana , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org References: <20241010124529.78460-1-y.oudjana@protonmail.com> <20241010124529.78460-3-y.oudjana@protonmail.com> Content-Language: en-US From: Yassine Oudjana In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 10/10/2024 3:59 pm, AngeloGioacchino Del Regno wrote: > Il 10/10/24 14:45, Yassine Oudjana ha scritto: >> From: Yassine Oudjana >> >> Add drivers for MT6735 apmixedsys, topckgen, infracfg and pericfg >> clock and reset controllers. These provide the base clocks and resets >> on the platform, enough to bring up all essential blocks including >> PWRAP, MSDC and peripherals (UART, I2C, SPI). >> >> Signed-off-by: Yassine Oudjana >> --- >>   MAINTAINERS                                  |   4 + >>   drivers/clk/mediatek/Kconfig                 |   9 + >>   drivers/clk/mediatek/Makefile                |   1 + >>   drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 138 +++++++ >>   drivers/clk/mediatek/clk-mt6735-infracfg.c   | 107 +++++ >>   drivers/clk/mediatek/clk-mt6735-pericfg.c    | 124 ++++++ >>   drivers/clk/mediatek/clk-mt6735-topckgen.c   | 394 +++++++++++++++++++ >>   7 files changed, 777 insertions(+) >>   create mode 100644 drivers/clk/mediatek/clk-mt6735-apmixedsys.c >>   create mode 100644 drivers/clk/mediatek/clk-mt6735-infracfg.c >>   create mode 100644 drivers/clk/mediatek/clk-mt6735-pericfg.c >>   create mode 100644 drivers/clk/mediatek/clk-mt6735-topckgen.c >> > > You're so, so, so, so..... *so close* to get this one upstream. > > Read the comments below and *please*, fix it and send a v6 *as soon as > you can*, > so that we get a good chance to see this in v6.13 and so that you can > move on > with upstreaming the other stuff that you got for this SoC. > > ..snip... > >> diff --git a/drivers/clk/mediatek/clk-mt6735-infracfg.c b/drivers/clk/ >> mediatek/clk-mt6735-infracfg.c >> new file mode 100644 >> index 0000000000000..eceb13af3222a >> --- /dev/null >> +++ b/drivers/clk/mediatek/clk-mt6735-infracfg.c >> @@ -0,0 +1,107 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Copyright (c) 2022 Yassine Oudjana >> + */ >> + >> +#include >> +#include >> + >> +#include "clk-gate.h" >> +#include "clk-mtk.h" >> + >> +#include >> +#include >> + >> +#define INFRA_RST0            0x30 >> +#define INFRA_GLOBALCON_PDN0        0x40 >> +#define INFRA_PDN1            0x44 >> +#define    INFRA_PDN_STA            0x48 > > #defineINFRA_PDN_STA .... I know this is a typo, but you'll have to > fix it. > > Please replace the tabulation with a space, so that this is consistent > with all > of the other definitions that you have in here. > >> + >> +#define RST_NR_PER_BANK            32 >> + > > ..snip.. > >> diff --git a/drivers/clk/mediatek/clk-mt6735-pericfg.c b/drivers/clk/ >> mediatek/clk-mt6735-pericfg.c >> new file mode 100644 >> index 0000000000000..6f298d5538782 >> --- /dev/null >> +++ b/drivers/clk/mediatek/clk-mt6735-pericfg.c >> @@ -0,0 +1,124 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Copyright (c) 2022 Yassine Oudjana >> + */ >> + >> +#include >> +#include >> + >> +#include "clk-gate.h" >> +#include "clk-mtk.h" >> + >> +#include >> +#include >> + >> +#define PERI_GLOBALCON_RST0        0x00 >> +#define PERI_GLOBALCON_RST1        0x04 >> +#define PERI_GLOBALCON_PDN0_SET        0x08 >> +#define PERI_GLOBALCON_PDN0_CLR        0x10 >> +#define    PERI_GLOBALCON_PDN0_STA        0x18 > > same here > >> + >> +#define RST_NR_PER_BANK            32 > After which: > > Reviewed-by: AngeloGioacchino Del Regno > Tried so hard to catch all typos but I guess some still had to make it through. One quick fix coming up!