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This >> enables proper clock management through the platform firmware instead >> of relying on static fixed-clock definitions. >> >> Add DT macro headers for Versal NET and base Versal clocks, power >> domains and resets that are required by the CCF clock dtsi. >> >> Signed-off-by: Michal Simek ... >> + firmware { >> + versal_net_firmware: versal-net-firmware { >> + compatible = "xlnx,versal-net-firmware", "xlnx,versal-firmware"; >> + bootph-all; >> + method = "smc"; >> + #power-domain-cells = <1>; >> + >> + versal_net_reset: reset-controller { >> + compatible = "xlnx,versal-net-reset"; >> + #reset-cells = <1>; >> + }; >> + >> + versal_net_clk: clock-controller { >> + bootph-all; >> + #clock-cells = <1>; >> + compatible = "xlnx,versal-net-clk", "xlnx,versal-clk"; >> + clocks = <&ref_clk>, <&ref_clk>, <&ref_clk>; >> + clock-names = "ref", "pl_alt_ref", "alt_ref"; >> + }; >> + >> + versal_net_power: power-management { /* untested */ >> + compatible = "xlnx,zynqmp-power"; >> + interrupt-parent = <&gic>; >> + interrupts = <0 57 4>; >> + mboxes = <&ipi_mailbox_pmu1 0>, >> + <&ipi_mailbox_pmu1 1>; >> + mbox-names = "tx", "rx"; >> + }; >> + }; >> + }; >> + >> + zynqmp-ipi { >> + compatible = "xlnx,zynqmp-ipi-mailbox"; >> + interrupt-parent = <&gic>; >> + interrupts = <0 57 4>; >> + xlnx,ipi-id = <2>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + >> + ipi_mailbox_pmu1: mailbox@eb3f0440 { >> + compatible = "xlnx,zynqmp-ipi-dest-mailbox"; >> + reg = <0 0xeb3f0440 0 0x20>, >> + <0 0xeb3f0460 0 0x20>, >> + <0 0xeb3f0280 0 0x20>, >> + <0 0xeb3f02a0 0 0x20>; >> + reg-names = "local_request_region", "local_response_region", >> + "remote_request_region", "remote_response_region"; >> + #mbox-cells = <1>; >> + xlnx,ipi-id = <1>; >> + }; >> + }; >> +}; >> + >> +&cpu0 { >> + clocks = <&versal_net_clk ACPU_0>; >> +}; > > This structure is unusual and not great for readability. Imagine if we > did a .dtsi for each provider with all the consumer properties. At early stages for the silicon are all clocks enabled because link to coprocessor is not validated yet that's why that fixed clock DTSI happened. And because at this stage power management is not important (because everything is on by default) that properties are not listed. That's why historially we had two files. One with fixed clock and second (with wrong ccf suffix) for firmware interface. In near future we are going to have (not for this cpu) also SCMI one. And because reset/power domain requires firmware node they are placed to the same file. And I will do that other changes in v2. Thanks, Michal