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([2a01:e0a:982:cbb0:740:b323:3531:5c75]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434d52c0dc8sm24581155e9.27.2024.12.04.05.31.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 04 Dec 2024 05:31:33 -0800 (PST) Message-ID: <02b6b148-90d8-4f9c-9a38-d0796c590d10@linaro.org> Date: Wed, 4 Dec 2024 14:31:32 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: neil.armstrong@linaro.org Reply-To: neil.armstrong@linaro.org Subject: Re: [PATCH v3] dmaengine: qcom: gpi: Add GPI immediate DMA support for SPI protocol To: Jyothi Kumar Seerapu , Vinod Koul Cc: linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, quic_msavaliy@quicinc.com, quic_vtanuku@quicinc.com References: <20241204122059.24239-1-quic_jseerapu@quicinc.com> <2c66c9df-49f1-42d5-8f80-27e36476e19b@linaro.org> <9c6127e3-17e1-4235-90b6-91f5dfa3166d@quicinc.com> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <9c6127e3-17e1-4235-90b6-91f5dfa3166d@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi, On 04/12/2024 14:29, Jyothi Kumar Seerapu wrote: > > > On 12/4/2024 6:19 PM, neil.armstrong@linaro.org wrote: >> Hi, >> >> On 04/12/2024 13:20, Jyothi Kumar Seerapu wrote: >>> The DMA TRE(Transfer ring element) buffer contains the DMA >>> buffer address. Accessing data from this address can cause >>> significant delays in SPI transfers, which can be mitigated to >>> some extent by utilizing immediate DMA support. >>> >>> QCOM GPI DMA hardware supports an immediate DMA feature for data >>> up to 8 bytes, storing the data directly in the DMA TRE buffer >>> instead of the DMA buffer address. This enhancement enables faster >>> SPI data transfers. >>> >>> This optimization reduces the average transfer time from 25 us to >>> 16 us for a single SPI transfer of 8 bytes length, with a clock >>> frequency of 50 MHz. >>> >>> Signed-off-by: Jyothi Kumar Seerapu >>> --- >>> >>> v2-> v3: >>>     - When to enable Immediate DMA support, control is moved to GPI driver >>>       from SPI driver. >>>     - Optimizations are done in GPI driver related to immediate dma changes. >>>     - Removed the immediate dma supported changes in qcom-gpi-dma.h file >>>       and handled in GPI driver. >>> >>>     Link to v2: >>>     https://lore.kernel.org/all/20241128133351.24593-2-quic_jseerapu@quicinc.com/ >>>     https://lore.kernel.org/all/20241128133351.24593-3-quic_jseerapu@quicinc.com/ >>> >>> v1 -> v2: >>>     - Separated the patches to dmaengine and spi subsystems >>>     - Removed the changes which are not required for this feature from >>>       qcom-gpi-dma.h file. >>>     - Removed the type conversions used in gpi_create_spi_tre. >>>     Link to v1: >>>     https://lore.kernel.org/lkml/20241121115201.2191-2-quic_jseerapu@quicinc.com/ >>> >>>   drivers/dma/qcom/gpi.c | 32 +++++++++++++++++++++++++++----- >>>   1 file changed, 27 insertions(+), 5 deletions(-) >>> >>> diff --git a/drivers/dma/qcom/gpi.c b/drivers/dma/qcom/gpi.c >>> index 52a7c8f2498f..35451d5a81f7 100644 >>> --- a/drivers/dma/qcom/gpi.c >>> +++ b/drivers/dma/qcom/gpi.c >>> @@ -27,6 +27,7 @@ >>>   #define TRE_FLAGS_IEOT        BIT(9) >>>   #define TRE_FLAGS_BEI        BIT(10) >>>   #define TRE_FLAGS_LINK        BIT(11) >>> +#define TRE_FLAGS_IMMEDIATE_DMA    BIT(16) >>>   #define TRE_FLAGS_TYPE        GENMASK(23, 16) >>>   /* SPI CONFIG0 WD0 */ >>> @@ -64,6 +65,7 @@ >>>   /* DMA TRE */ >>>   #define TRE_DMA_LEN        GENMASK(23, 0) >>> +#define TRE_DMA_IMMEDIATE_LEN    GENMASK(3, 0) >>>   /* Register offsets from gpi-top */ >>>   #define GPII_n_CH_k_CNTXT_0_OFFS(n, k)    (0x20000 + (0x4000 * (n)) + (0x80 * (k))) >>> @@ -1711,6 +1713,8 @@ static int gpi_create_spi_tre(struct gchan *chan, struct gpi_desc *desc, >>>       dma_addr_t address; >>>       struct gpi_tre *tre; >>>       unsigned int i; >>> +    int len; >>> +    u8 immediate_dma; >> >> Should be bool > Hi Neil, Thanks for the review. > Sure, will change it to bool. >> >>>       /* first create config tre if applicable */ >>>       if (direction == DMA_MEM_TO_DEV && spi->set_config) { >>> @@ -1763,14 +1767,32 @@ static int gpi_create_spi_tre(struct gchan *chan, struct gpi_desc *desc, >>>       tre_idx++; >>>       address = sg_dma_address(sgl); >>> -    tre->dword[0] = lower_32_bits(address); >>> -    tre->dword[1] = upper_32_bits(address); >>> +    len = sg_dma_len(sgl); >>> -    tre->dword[2] = u32_encode_bits(sg_dma_len(sgl), TRE_DMA_LEN); >>> +    immediate_dma = (direction == DMA_MEM_TO_DEV) && len <= 2 * sizeof(tre->dword[0]); >> >> I would have added () around 2 * sizeof(tre->dword[0]) > > Below condition is fine or should i add brackets ? > > immediate_dma = direction == DMA_MEM_TO_DEV && >                 len <= 2 * sizeof(tre->dword[0]); This is what Dmitry requested, it's fine for me. Neil >> >>> + >>> +    /* Support Immediate dma for write transfers for data length up to 8 bytes */ >>> +    if (immediate_dma) { >>> +        /* >>> +         * For Immediate dma, data length may not always be length of 8 bytes, >>> +         * it can be length less than 8, hence initialize both dword's with 0 >>> +         */ >>> +        tre->dword[0] = 0; >>> +        tre->dword[1] = 0; >>> +        memcpy(&tre->dword[0], sg_virt(sgl), len); >>> + >>> +        tre->dword[2] = u32_encode_bits(len, TRE_DMA_IMMEDIATE_LEN); >>> +    } else { >>> +        tre->dword[0] = lower_32_bits(address); >>> +        tre->dword[1] = upper_32_bits(address); >>> + >>> +        tre->dword[2] = u32_encode_bits(len, TRE_DMA_LEN); >>> +    } >>>       tre->dword[3] = u32_encode_bits(TRE_TYPE_DMA, TRE_FLAGS_TYPE); >>> -    if (direction == DMA_MEM_TO_DEV) >>> -        tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_IEOT); >>> +    tre->dword[3] |= u32_encode_bits(!!immediate_dma, TRE_FLAGS_IMMEDIATE_DMA); >> >> And you can drop !! if it's a bool > Sure thanks, i will drop !! in V4. >> >>> +    tre->dword[3] |= u32_encode_bits(!!(direction == DMA_MEM_TO_DEV), >>> +                     TRE_FLAGS_IEOT); >> >> I thingk you can drop !! here aswell, the check will return a bool > Sure thanks, i will drop !! in V4. >> >>>       for (i = 0; i < tre_idx; i++) >>>           dev_dbg(dev, "TRE:%d %x:%x:%x:%x\n", i, desc->tre[i].dword[0], >> >> Otherwise I like the simplification :-) > Thanks, i will incorporate the changes in V4. >> >> Thanks, >> Neil