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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a99102a998esm198244466b.94.2024.10.04.02.28.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 04 Oct 2024 02:28:02 -0700 (PDT) Message-ID: <02ded4a4-0f0f-4a96-afd9-5a1756215382@oss.qualcomm.com> Date: Fri, 4 Oct 2024 11:28:00 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] arm64: dts: qcom: x1e80100: Switch PCIe 6a to 4 lanes mode To: Abel Vesa , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Johan Hovold , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20241004-x1e80100-dts-fixes-pcie6a-v2-1-3af9ff7a5a71@linaro.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20241004-x1e80100-dts-fixes-pcie6a-v2-1-3af9ff7a5a71@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: F1bSx_h1CJyD4_dlX8O0m7VUmSdTJfKJ X-Proofpoint-GUID: F1bSx_h1CJyD4_dlX8O0m7VUmSdTJfKJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 mlxscore=0 priorityscore=1501 phishscore=0 bulkscore=0 impostorscore=0 malwarescore=0 suspectscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410040068 On 4.10.2024 11:06 AM, Abel Vesa wrote: > The PCIe 6a controller and PHY can be configured in 4-lanes mode or > 2-lanes mode. For 4-lanes mode, it fetches the lanes provided by PCIe 6b. > For 2-lanes mode, PCIe 6a uses 2 lanes and then PCIe 6b uses the other 2 > lanes. Configure it in 4-lane mode and then each board can configure it > depending on the design. Both the QCP and CRD boards, currently upstream, > use PCIe 6a for NVMe in 4-lane mode. Mark the controller as 4-lane as > well. This is the last change needed in order to support NVMe with Gen4 > 4-lanes on all existing X Elite boards. > > Signed-off-by: Abel Vesa > --- > Changes in v2: > - Re-worded the commit message according to Johan's suggestions > - Dropped the clocks changes. > - Dropped the fixes tag as this relies on the Gen4 4-lanes stability > patchset which has been only merged in 6.12, so backporting this patch > would break NVMe support for all platforms. > - Link to v1: https://lore.kernel.org/r/20240531-x1e80100-dts-fixes-pcie6a-v1-2-1573ebcae1e8@linaro.org > --- Depends on https://lore.kernel.org/linux-arm-msm/20240916082307.29393-3-johan+linaro@kernel.org/ Otherwise Reviewed-by: Konrad Dybcio Konrad