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Wysocki" , Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Atish Patra , Andrew Jones , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Message-Id: <031395FE-C51C-45A7-85A3-CC4A25EB6066@gmail.com> References: <20250820152316.1012757-1-apatel@ventanamicro.com> To: Anup Patel X-Mailer: Apple Mail (2.3864.100.1.1.5) > On Aug 20, 2025, at 23:23, Anup Patel wrote: >=20 > The pgprot_dmacoherent() is used when allocating memory for > non-coherent devices and by default pgprot_dmacoherent() is > same as pgprot_noncached() unless architecture overrides it. >=20 > Currently, there is no pgprot_dmacoherent() definition for > RISC-V hence non-coherent device memory is being mapped as > IO thereby making CPU access to such memory slow. >=20 > Define pgprot_dmacoherent() to be same as pgprot_writecombine() > for RISC-V so that CPU access non-coherent device memory as > NOCACHE which is better than accessing it as IO. >=20 > Fixes: ff689fd21cb1 ("riscv: add RISC-V Svpbmt extension support") > Signed-off-by: Anup Patel Tested-by: Han Gao > --- > arch/riscv/include/asm/pgtable.h | 2 ++ > 1 file changed, 2 insertions(+) >=20 > diff --git a/arch/riscv/include/asm/pgtable.h = b/arch/riscv/include/asm/pgtable.h > index 91697fbf1f90..00d8bdaf1e8d 100644 > --- a/arch/riscv/include/asm/pgtable.h > +++ b/arch/riscv/include/asm/pgtable.h > @@ -653,6 +653,8 @@ static inline pgprot_t = pgprot_writecombine(pgprot_t _prot) > return __pgprot(prot); > } >=20 > +#define pgprot_dmacoherent pgprot_writecombine > + > /* > * Both Svade and Svadu control the hardware behavior when the PTE A/D = bits need to be set. By > * default the M-mode firmware enables the hardware updating scheme = when only Svadu is present in > --=20 > 2.43.0 >=20 >=20 > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv >=20