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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjIyMDEyMCBTYWx0ZWRfX9gg+wV2Q4NRE gaXdv6Uu1PxTdFpG/DieNcI1P3M/pALQTgFig3GO7dRBC/lOCh7x8820CchiB16Q3ZlP7NII3tU EOqJMwv3tcPrs8OP8YxxDcCK3UWcIwdAvqzDm5y7je02TCV6f9C++n+oUs81rcC4J4Y3X7/ojbh SGk0wLh3oG2mcLPcXMAEtviW86SriEapEOhmOzGZ9Mhp8nR8QjJ/PwFfrvBlbKqiCI5YlYJ4S4Y P9XAktxX2vMUlVZCgFqe/ajMq4rv3tRTnamijFFJdrH8JlsqH+hNWfk2xkndbwAMREz5ovkHD64 FYQE+mJVgx/sa/dk0RHlHT5IHOo5nbQ2rruutocKa7r9Urin8avSA04joE3TrGnqv8cpCVIOqhO U9pr0tVu+Xt+mgPwV1ScgbcooD6+zW7/1d9YvskgEcI7/2PKb9ZcIKkrwDYmvH+MMfAIIDNYKba dzrwh9N8ag7C4VLVXsw== X-Proofpoint-ORIG-GUID: NZyDdQfrtOocwYrO3aHUdX-x3oCH3_8n X-Proofpoint-Spam-Info: AW1haW4tMjYwNjIyMDEyMCBTYWx0ZWRfX934vqZAZZi9d JOKhiDJCmbycfe/IvJA7oxUDNdPLNAq/luWd6Obhd6eef3M+tGCMx5RVj1U67EMkHCEWKXNRSK8 JKO0W44wsEFJfc6O4MvyZaEN7h3YKy4= X-Authority-Analysis: v=2.4 cv=YtA/gYYX c=1 sm=1 tr=0 ts=6a3926e7 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=tIU0ZN1R_etRVKZmDSAA:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-GUID: NZyDdQfrtOocwYrO3aHUdX-x3oCH3_8n X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-22_02,2026-06-18_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 adultscore=0 suspectscore=0 clxscore=1015 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606220120 On 6/22/26 7:11 AM, Qiang Yu wrote: > Before XO refclk is distributed to PCIe/USB/eDP PHYs, it passes through > a QREF block. QREF is powered by dedicated LDO rails, and the clkref_en > register controls whether refclk is gated through to the PHY side. > > These clkref controls are different from typical GCC branch clocks: > - only a single enable bit is present, without branch-style config bits > - regulators must be voted before enable and unvoted after disable > > Model this as a dedicated clk_ref clock type with custom clk_ops instead > of reusing struct clk_branch semantics. > > Also provide a common registration/probe API so the same clkref model > can be reused regardless of where clkref_en registers are placed, e.g. > TCSR on glymur and TLMM on SM8750. > > Signed-off-by: Qiang Yu > --- [...] > + for (clk_idx = 0; clk_idx < num_clk_refs; clk_idx++) { > + clk_ref = &clk_refs[clk_idx]; > + desc = &descs[clk_idx]; > + > + if (!desc->name) > + continue; Carrying over from the previous discussion: > // this allows "holes" in dt-bindings for $reasons > if (!desc) > continue; > > // this makes sure the programmer did not omit something important > // while not taking the entire system down > if (WARN_ON(!desc->name) > continue; > The NULL name check is intentional - the descriptor array is indexed by clock ID, and mahua has fewer clocks than glymur, leaving holes at certain indices. So this is expected at runtime. WARN_ON would be noise log here. -> Your worry is captured by nullchecking `desc` (i.e. descs[clk_idx]) because in the mahua case we've got (ephemeral indices) tcsr_cc_mahua_clk_descs[] = { [0] = { foo }, // [1] is unassigned - OK [2] = { bar }, }; while (!desc->name) checks for: tcsr_cc_mahua_clk_descs[] = { [0] = { .name = "foo", .offset = 0x10 }, // name is NULL by virtue of partial struct initialization [1] = { .offset = 0x20 }, }; however I overlooked that we actually just have a normal array of structs.. if we turn it into a struct pointer array with assigmnents like: [TCSR_EDP_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { .name = "foo", ... }; we can achieve that Konrad