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([2a01:e0a:982:cbb0:84a5:7e09:b15:f1fe]) by smtp.gmail.com with ESMTPSA id fn9-20020a05600c688900b003cf6a55d8e8sm5100190wmb.7.2022.11.25.04.59.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 25 Nov 2022 04:59:10 -0800 (PST) Message-ID: <038bebc1-2999-69d0-9c3d-e25acf61e31d@linaro.org> Date: Fri, 25 Nov 2022 13:59:09 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 From: Neil Armstrong Reply-To: neil.armstrong@linaro.org Subject: Re: [PATCH 3/6] soc: amlogic: meson-pwrc: Add NNA power domain for A311D Content-Language: en-US To: Tomeu Vizoso Cc: Kevin Hilman , Jerome Brunet , Martin Blumenstingl , "moderated list:ARM/Amlogic Meson SoC support" , "open list:ARM/Amlogic Meson SoC support" , open list References: <20221125111921.37261-1-tomeu.vizoso@collabora.com> <20221125111921.37261-4-tomeu.vizoso@collabora.com> Organization: Linaro Developer Services In-Reply-To: <20221125111921.37261-4-tomeu.vizoso@collabora.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 25/11/2022 12:19, Tomeu Vizoso wrote: > Based on power initialization sequence in downstream driver. > > Signed-off-by: Tomeu Vizoso > --- > drivers/soc/amlogic/meson-ee-pwrc.c | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/drivers/soc/amlogic/meson-ee-pwrc.c b/drivers/soc/amlogic/meson-ee-pwrc.c > index dd5f2a13ceb5..925cfaf50d11 100644 > --- a/drivers/soc/amlogic/meson-ee-pwrc.c > +++ b/drivers/soc/amlogic/meson-ee-pwrc.c > @@ -46,6 +46,9 @@ > #define HHI_NANOQ_MEM_PD_REG1 (0x47 << 2) > #define HHI_VPU_MEM_PD_REG2 (0x4d << 2) > > +#define G12A_HHI_NANOQ_MEM_PD_REG0 (0x43 << 2) > +#define G12A_HHI_NANOQ_MEM_PD_REG1 (0x44 << 2) > + > struct meson_ee_pwrc; > struct meson_ee_pwrc_domain; > > @@ -106,6 +109,13 @@ static struct meson_ee_pwrc_top_domain sm1_pwrc_usb = SM1_EE_PD(17); > static struct meson_ee_pwrc_top_domain sm1_pwrc_pci = SM1_EE_PD(18); > static struct meson_ee_pwrc_top_domain sm1_pwrc_ge2d = SM1_EE_PD(19); > > +static struct meson_ee_pwrc_top_domain g12a_pwrc_nna = { \ > + .sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0, \ > + .sleep_mask = BIT(16) | BIT(17), \ > + .iso_reg = GX_AO_RTI_GEN_PWR_ISO0, \ > + .iso_mask = BIT(16) | BIT(17), \ > + }; > + > /* Memory PD Domains */ > > #define VPU_MEMPD(__reg) \ > @@ -217,6 +227,11 @@ static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = { > { HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) }, > }; > > +static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_nna[] = { > + { G12A_HHI_NANOQ_MEM_PD_REG0, 0xffffffff }, > + { G12A_HHI_NANOQ_MEM_PD_REG1, 0xffffffff }, Weird it's not 0xff like on SM1, I looked at the A311D Datasheet and HHI_NANOQ_MEM_PD_REG0 is 31:0 so 0xffffffff is correct, but HHI_NANOQ_MEM_PD_REG1 is 23:0 so 0xFFFFFF is the correct value. Bur please replace with GENMASK(31, 0) and GENMASK(23, 0) to align with the rest of the code. > +}; > + > #define VPU_PD(__name, __top_pd, __mem, __is_pwr_off, __resets, __clks) \ > { \ > .name = __name, \ > @@ -253,6 +268,8 @@ static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = { > [PWRC_G12A_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, g12a_pwrc_mem_vpu, > pwrc_ee_is_powered_off, 11, 2), > [PWRC_G12A_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth), > + [PWRC_G12A_NNA_ID] = TOP_PD("NNA", &g12a_pwrc_nna, g12a_pwrc_mem_nna, > + pwrc_ee_is_powered_off), > }; > > static struct meson_ee_pwrc_domain_desc gxbb_pwrc_domains[] = { With this fixed: Reviewed-by: Neil Armstrong Thanks, Neil