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([2a01:e0a:106d:1080:a12d:6e5e:e745:c5e8]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4855642c481sm82514775e9.10.2026.03.16.01.30.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 16 Mar 2026 01:30:45 -0700 (PDT) Message-ID: <03edfc8f-d7e3-4caf-95cc-7c5efb1d1f49@linaro.org> Date: Mon, 16 Mar 2026 09:30:46 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Reply-To: Neil Armstrong Subject: Re: [PATCH v2 03/11] arm64: dts: qcom: x1e80100: Add CAMSS block definition To: Bryan O'Donoghue , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260316-x1e-camss-csi2-phy-dtsi-v2-0-859f3fa55790@linaro.org> <20260316-x1e-camss-csi2-phy-dtsi-v2-3-859f3fa55790@linaro.org> From: Neil Armstrong Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 3/16/26 02:12, Bryan O'Donoghue wrote: > Add dtsi to describe the xe180100 CAMSS block > > 4 x CSIPHY > 3 x TPG > 2 x CSID > 2 x CSID Lite > 2 x IFE > 2 x IFE Lite > > Signed-off-by: Bryan O'Donoghue > --- > arch/arm64/boot/dts/qcom/hamoa.dtsi | 367 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 367 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi > index 38f9da6ad9ca5..c62187856a451 100644 > --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi > +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi > @@ -16,6 +16,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -5543,6 +5544,372 @@ cci1_i2c1: i2c-bus@1 { > }; > }; > > + camss: isp@acb7000 { > + compatible = "qcom,x1e80100-camss", "simple-mfd"; > + > + reg = <0 0x0acb7000 0 0x2000>, > + <0 0x0acb9000 0 0x2000>, > + <0 0x0acbb000 0 0x2000>, > + <0 0x0acc6000 0 0x1000>, > + <0 0x0acca000 0 0x1000>, > + <0 0x0acb6000 0 0x1000>, > + <0 0x0ace4000 0 0x1000>, > + <0 0x0ace6000 0 0x1000>, > + <0 0x0ace8000 0 0x1000>, > + <0 0x0acec000 0 0x4000>, > + <0 0x0acf6000 0 0x1000>, > + <0 0x0acf7000 0 0x1000>, > + <0 0x0acf8000 0 0x1000>, > + <0 0x0ac62000 0 0xf000>, > + <0 0x0ac71000 0 0xf000>, > + <0 0x0acc7000 0 0x2000>, > + <0 0x0accb000 0 0x2000>; > + > + reg-names = "csid0", > + "csid1", > + "csid2", > + "csid_lite0", > + "csid_lite1", > + "csid_wrapper", > + "csiphy0", > + "csiphy1", > + "csiphy2", > + "csiphy4", > + "csitpg0", > + "csitpg1", > + "csitpg2", > + "vfe0", > + "vfe1", > + "vfe_lite0", > + "vfe_lite1"; > + > + clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, > + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, > + <&camcc CAM_CC_CORE_AHB_CLK>, > + <&camcc CAM_CC_CPAS_AHB_CLK>, > + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, > + <&camcc CAM_CC_CPAS_IFE_0_CLK>, > + <&camcc CAM_CC_CPAS_IFE_1_CLK>, > + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, > + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, > + <&camcc CAM_CC_CSID_CLK>, > + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, > + <&camcc CAM_CC_CSIPHY0_CLK>, > + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, > + <&camcc CAM_CC_CSIPHY1_CLK>, > + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, > + <&camcc CAM_CC_CSIPHY2_CLK>, > + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, > + <&camcc CAM_CC_CSIPHY4_CLK>, > + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, > + <&gcc GCC_CAMERA_HF_AXI_CLK>, > + <&gcc GCC_CAMERA_SF_AXI_CLK>, > + <&camcc CAM_CC_IFE_0_CLK>, > + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, > + <&camcc CAM_CC_IFE_1_CLK>, > + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, > + <&camcc CAM_CC_IFE_LITE_CLK>, > + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, > + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, > + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; > + > + clock-names = "camnoc_nrt_axi", > + "camnoc_rt_axi", > + "core_ahb", > + "cpas_ahb", > + "cpas_fast_ahb", > + "cpas_vfe0", > + "cpas_vfe1", > + "cpas_vfe_lite", > + "cphy_rx_clk_src", > + "csid", > + "csid_csiphy_rx", > + "csiphy0", > + "csiphy0_timer", > + "csiphy1", > + "csiphy1_timer", > + "csiphy2", > + "csiphy2_timer", > + "csiphy4", > + "csiphy4_timer", > + "gcc_axi_hf", > + "gcc_axi_sf", > + "vfe0", > + "vfe0_fast_ahb", > + "vfe1", > + "vfe1_fast_ahb", > + "vfe_lite", > + "vfe_lite_ahb", > + "vfe_lite_cphy_rx", > + "vfe_lite_csid"; > + > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + > + interrupt-names = "csid0", > + "csid1", > + "csid2", > + "csid_lite0", > + "csid_lite1", > + "csiphy0", > + "csiphy1", > + "csiphy2", > + "csiphy4", > + "vfe0", > + "vfe1", > + "vfe_lite0", > + "vfe_lite1"; > + > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY > + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, > + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "ahb", > + "hf_mnoc", > + "sf_mnoc", > + "sf_icp_mnoc"; > + > + iommus = <&apps_smmu 0x800 0x60>, > + <&apps_smmu 0x820 0x60>, > + <&apps_smmu 0x840 0x60>, > + <&apps_smmu 0x860 0x60>, > + <&apps_smmu 0x18a0 0x0>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + phys = <&csiphy0 PHY_TYPE_DPHY>, <&csiphy1 PHY_TYPE_DPHY>, > + <&csiphy2 PHY_TYPE_DPHY>, <&csiphy4 PHY_TYPE_DPHY>; > + phy-names = "csiphy0", "csiphy1", > + "csiphy2", "csiphy4"; Adding a separate node for PHYs and adding them in a a fixed phys property is not what I would call an evolution, it will still require a per-platform data to associate a phy-name to a PHY port... just add port/endpoint to link each camss port to each phy and make this dynamic. Neil > + > + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, > + <&camcc CAM_CC_IFE_1_GDSC>, > + <&camcc CAM_CC_TITAN_TOP_GDSC>; > + power-domain-names = "ife0", > + "ife1", > + "top"; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + #address-cells = <1>; > + #size-cells = <0>; > + camss_csiphy0_inep0: endpoint@0 { > + reg = <0>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + camss_csiphy1_inep0: endpoint@0 { > + reg = <0>; > + }; > + }; > + > + port@2 { > + reg = <2>; > + #address-cells = <1>; > + #size-cells = <0>; > + camss_csiphy2_inep0: endpoint@0 { > + reg = <0>; > + }; > + }; > + > + port@3 { > + reg = <3>; > + #address-cells = <1>; > + #size-cells = <0>; > + camss_csiphy4_inep0: endpoint@0 { > + reg = <0>; > + }; > + }; > + }; > + > + csiphy0: phy@ace4000 { > + compatible = "qcom,x1e80100-csi2-phy"; > + reg = <0 0x0ace4000 0 0x2000>; > + > + clocks = <&camcc CAM_CC_CSIPHY0_CLK>, > + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, > + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, > + <&camcc CAM_CC_CPAS_AHB_CLK>; > + clock-names = "csiphy", > + "csiphy_timer", > + "camnoc_axi", > + "cpas_ahb"; > + > + operating-points-v2 = <&csiphy_mxc_opp_table>; > + > + interrupts = ; > + > + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>, > + <&rpmhpd RPMHPD_MXC>, > + <&rpmhpd RPMHPD_MMCX>; > + power-domain-names = "top", > + "mx", > + "mmcx"; > + > + #phy-cells = <1>; > + > + status = "disabled"; > + }; > + > + csiphy1: phy@ace6000 { > + compatible = "qcom,x1e80100-csi2-phy"; > + reg = <0 0x0ace6000 0 0x2000>; > + > + clocks = <&camcc CAM_CC_CSIPHY1_CLK>, > + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, > + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, > + <&camcc CAM_CC_CPAS_AHB_CLK>; > + clock-names = "csiphy", > + "csiphy_timer", > + "camnoc_axi", > + "cpas_ahb"; > + > + operating-points-v2 = <&csiphy_mxc_opp_table>; > + > + interrupts = ; > + > + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>, > + <&rpmhpd RPMHPD_MXC>, > + <&rpmhpd RPMHPD_MMCX>; > + power-domain-names = "top", > + "mx", > + "mmcx"; > + > + #phy-cells = <1>; > + > + status = "disabled"; > + }; > + > + csiphy2: phy@ace8000 { > + compatible = "qcom,x1e80100-csi2-phy"; > + reg = <0 0x0ace8000 0 0x2000>; > + > + clocks = <&camcc CAM_CC_CSIPHY2_CLK>, > + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, > + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, > + <&camcc CAM_CC_CPAS_AHB_CLK>; > + clock-names = "csiphy", > + "csiphy_timer", > + "camnoc_axi", > + "cpas_ahb"; > + > + operating-points-v2 = <&csiphy_mxc_opp_table>; > + > + interrupts = ; > + > + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>, > + <&rpmhpd RPMHPD_MXC>, > + <&rpmhpd RPMHPD_MMCX>; > + power-domain-names = "top", > + "mx", > + "mmcx"; > + > + #phy-cells = <1>; > + > + status = "disabled"; > + }; > + > + csiphy4: phy@acec000 { > + compatible = "qcom,x1e80100-csi2-phy"; > + reg = <0 0x0acec000 0 0x2000>; > + > + clocks = <&camcc CAM_CC_CSIPHY4_CLK>, > + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, > + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, > + <&camcc CAM_CC_CPAS_AHB_CLK>; > + clock-names = "csiphy", > + "csiphy_timer", > + "camnoc_axi", > + "cpas_ahb"; > + > + operating-points-v2 = <&csiphy_mxa_opp_table>; > + > + interrupts = ; > + > + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>, > + <&rpmhpd RPMHPD_MX>, > + <&rpmhpd RPMHPD_MMCX>; > + power-domain-names = "top", > + "mx", > + "mmcx"; > + > + #phy-cells = <1>; > + > + status = "disabled"; > + }; > + > + csiphy_mxc_opp_table: opp-table-mxc { > + compatible = "operating-points-v2"; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&rpmhpd_opp_low_svs_d1>, > + <&rpmhpd_opp_low_svs_d1>; > + }; > + > + opp-400000000 { > + opp-hz = /bits/ 64 <400000000>; > + required-opps = <&rpmhpd_opp_low_svs>, > + <&rpmhpd_opp_low_svs>; > + }; > + > + opp-480000000 { > + opp-hz = /bits/ 64 <480000000>; > + required-opps = <&rpmhpd_opp_low_svs>, > + <&rpmhpd_opp_low_svs>; > + }; > + }; > + > + csiphy_mxa_opp_table: opp-table-mxa { > + compatible = "operating-points-v2"; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&rpmhpd_opp_low_svs_d1>, > + <&rpmhpd_opp_low_svs_d1>; > + }; > + > + opp-400000000 { > + opp-hz = /bits/ 64 <400000000>; > + required-opps = <&rpmhpd_opp_low_svs>, > + <&rpmhpd_opp_low_svs>; > + }; > + > + opp-480000000 { > + opp-hz = /bits/ 64 <480000000>; > + required-opps = <&rpmhpd_opp_low_svs>, > + <&rpmhpd_opp_low_svs>; > + }; > + }; > + }; > + > camcc: clock-controller@ade0000 { > compatible = "qcom,x1e80100-camcc"; > reg = <0 0x0ade0000 0 0x20000>; >