From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from vps0.lunn.ch (vps0.lunn.ch [156.67.10.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D315E3BE623; Sun, 4 Oct 2026 21:20:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=156.67.10.101 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791148829; cv=none; b=pH5R9ZNAJK0D1xszlApaTlSF4BmIsXxksFdC7tHTYKTCOPnVziJIPm4RqmZcrX3Q/UbABMRJwjywfVyXlehJafr34T1gjCO6s18ASz4tDNCHN2gVxCxO63ce+7QlzMX7SIMyulm3RiB6tO4+bbSQfF0cVX6eDI/WpJ0W9goV5mI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791148829; c=relaxed/simple; bh=CtiR6RTTgvHxUzFtt8wEx+ek79goFpD8kk1JwXTSTWg=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=LozWkECZclWTtmWw2q7C3umLlTUqf+A4/PkdYmN3DaHzLdayhA/5HQ6nf69+LOrT6m0RFFKgfpHuem/PmjnKzI8T+8HZ6+y79sG68rMz2SAimFiS3XUEAx+7SrKRRN1iJQ0FejT35G/lXQBuNr5SKTQ1z+65OcLOaJGssEwsJTY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch; spf=pass smtp.mailfrom=lunn.ch; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b=4wLuTMe1; arc=none smtp.client-ip=156.67.10.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=lunn.ch Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b="4wLuTMe1" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=fj17ivJKl9pVttgkUPXykC072wjB1hkYn8FIT+/LeyI=; b=4wLuTMe1d8yvLRI010S0CAOWDM VA6PoB7vGuqU8PUyQoPhHLiggoc2cNtRZFZBcJIMAIoYNB7ki2wkTWXVoW0/K3nTrIFH3HOrfHOWK ETWMpyp9PvaI1x5F90Yftk4Z+IKvZWzEIGRpOVHIs8IFVkZJJDwXGbZF8VS7cL/KSsoc=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1xDTcn-008wXc-HL; Sun, 04 Oct 2026 23:20:01 +0200 Date: Sun, 4 Oct 2026 23:20:01 +0200 From: Andrew Lunn To: Dawid Glazik Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, maciej.lawniczak@intel.com Subject: Re: [PATCH 3/4] ARM: dts: aspeed: add Intel AVCRP BMC Message-ID: <04355d4a-e1db-4681-bca2-43806216a7fd@lunn.ch> References: <9dadaaf04cae28e13057fa5d65023789f74483fb.1790344811.git.dawid.glazik@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <9dadaaf04cae28e13057fa5d65023789f74483fb.1790344811.git.dawid.glazik@linux.intel.com> > +&mdio1 { > + status = "okay"; > + > + ethphy1: ethernet-phy@0 { > + compatible = "ethernet-phy-id001c.c916"; > + reg = <0>; > + reset-gpios = <&gpio0 ASPEED_GPIO(C, 1) GPIO_ACTIVE_LOW>; > + reset-assert-us = <10000>; > + reset-deassert-us = <50000>; > + }; > +}; > + > +&mac1 { > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_rgmii2_default>; > + clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>, > + <&syscon ASPEED_CLK_MAC2RCLK>; > + clock-names = "MACCLK", "RCLK"; > + phy-mode = "rgmii-id"; > + phy-handle = <ðphy1>; > +}; Oh, wow. Somebody actually got RGMII delays correct on the first try for an aspeed board. For these two nodes only: Reviewed-by: Andrew Lunn Andrew