From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF62CC433F5 for ; Wed, 5 Sep 2018 10:22:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4A6D72075C for ; Wed, 5 Sep 2018 10:22:43 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4A6D72075C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727883AbeIEOwI (ORCPT ); Wed, 5 Sep 2018 10:52:08 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:25936 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727572AbeIEOwH (ORCPT ); Wed, 5 Sep 2018 10:52:07 -0400 X-UUID: 852397d653e048c0955a12a45758804e-20180905 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1338094462; Wed, 05 Sep 2018 18:22:27 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Wed, 5 Sep 2018 18:22:25 +0800 Received: from mtkslt306.mediatek.inc (10.21.14.136) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Wed, 5 Sep 2018 18:22:25 +0800 From: Ryder Lee To: Matthias Brugger CC: Sean Wang , Roy Luo , Weijie Gao , , , , , Ryder Lee , CK Hu , chunhui dai , Bibby Hsieh Subject: [PATCH 5/5] arm: dts: mt7623: add display subsystem related device nodes Date: Wed, 5 Sep 2018 18:22:21 +0800 Message-ID: <0452ad90c2d18442d8b4ad32cdcdb56db74d40f0.1536141302.git.ryder.lee@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <84011aa94dd7be9239b7a2f944dd30fc70568fbb.1536141302.git.ryder.lee@mediatek.com> References: <84011aa94dd7be9239b7a2f944dd30fc70568fbb.1536141302.git.ryder.lee@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add display subsystem related device nodes for MT7623. Cc: CK Hu Signed-off-by: chunhui dai Signed-off-by: Bibby Hsieh Signed-off-by: Ryder Lee --- This patch depends on the series: https://lkml.org/lkml/2018/9/5/223 Hi Matthias, I know you're working on broken MMSYS - just want to ask whether it's possible to let the patch to go to your tree (if others are okay with it), and we could send another fixup one for MT7623 MMSYS later? --- arch/arm/boot/dts/mt7623.dtsi | 177 ++++++++++++++++++++++++++ arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 83 ++++++++++++ arch/arm/boot/dts/mt7623n-rfb-emmc.dts | 83 ++++++++++++ 3 files changed, 343 insertions(+) diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index d01bdee..c6e1e5b 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -23,6 +23,11 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + rdma0 = &rdma0; + rdma1 = &rdma1; + }; + cpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-shared; @@ -311,6 +316,25 @@ clock-names = "spi", "wrap"; }; + mipi_tx0: mipi-dphy@10010000 { + compatible = "mediatek,mt7623-mipi-tx", + "mediatek,mt2701-mipi-tx"; + reg = <0 0x10010000 0 0x90>; + clocks = <&clk26m>; + clock-output-names = "mipi_tx0_pll"; + #clock-cells = <0>; + #phy-cells = <0>; + }; + + cec: cec@10012000 { + compatible = "mediatek,mt7623-cec", + "mediatek,mt8173-cec"; + reg = <0 0x10012000 0 0xbc>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_CEC>; + status = "disabled"; + }; + cir: cir@10013000 { compatible = "mediatek,mt7623-cir"; reg = <0 0x10013000 0 0x1000>; @@ -359,6 +383,18 @@ #clock-cells = <1>; }; + hdmi_phy: phy@10209100 { + compatible = "mediatek,mt7623-hdmi-phy", + "mediatek,mt2701-hdmi-phy"; + reg = <0 0x10209100 0 0x24>; + clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; + clock-names = "pll_ref"; + clock-output-names = "hdmitx_dig_cts"; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; + rng: rng@1020f000 { compatible = "mediatek,mt7623-rng"; reg = <0 0x1020f000 0 0x1000>; @@ -505,6 +541,16 @@ status = "disabled"; }; + hdmiddc0: i2c@11013000 { + compatible = "mediatek,mt7623-hdmi-ddc", + "mediatek,mt8173-hdmi-ddc"; + interrupts = ; + reg = <0 0x11013000 0 0x1C>; + clocks = <&pericfg CLK_PERI_I2C3>; + clock-names = "ddc-i2c"; + status = "disabled"; + }; + thermal: thermal@1100b000 { #thermal-sensor-cells = <1>; compatible = "mediatek,mt7623-thermal", @@ -732,6 +778,84 @@ #clock-cells = <1>; }; + display_components: dispsys@14000000 { + compatible = "mediatek,mt7623-mmsys", + "mediatek,mt2701-mmsys"; + reg = <0 0x14000000 0 0x1000>; + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; + }; + + ovl@14007000 { + compatible = "mediatek,mt7623-disp-ovl", + "mediatek,mt2701-disp-ovl"; + reg = <0 0x14007000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_OVL>; + iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>; + mediatek,larb = <&larb0>; + }; + + rdma0: rdma@14008000 { + compatible = "mediatek,mt7623-disp-rdma", + "mediatek,mt2701-disp-rdma"; + reg = <0 0x14008000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_RDMA>; + iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>; + mediatek,larb = <&larb0>; + }; + + wdma@14009000 { + compatible = "mediatek,mt7623-disp-wdma", + "mediatek,mt2701-disp-wdma"; + reg = <0 0x14009000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_WDMA>; + iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>; + mediatek,larb = <&larb0>; + }; + + bls: bls@1400a000 { + compatible = "mediatek,mt7623-disp-pwm", + "mediatek,mt2701-disp-pwm"; + reg = <0 0x1400a000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&mmsys CLK_MM_MDP_BLS_26M>, + <&mmsys CLK_MM_DISP_BLS>; + clock-names = "main", "mm"; + status = "disabled"; + }; + + color@1400b000 { + compatible = "mediatek,mt7623-disp-color", + "mediatek,mt2701-disp-color"; + reg = <0 0x1400b000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_COLOR>; + }; + + dsi: dsi@1400c000 { + compatible = "mediatek,mt7623-dsi", + "mediatek,mt2701-dsi"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DSI_ENGINE>, + <&mmsys CLK_MM_DSI_DIG>, + <&mipi_tx0>; + clock-names = "engine", "digital", "hs"; + phys = <&mipi_tx0>; + phy-names = "dphy"; + status = "disabled"; + }; + + mutex: mutex@1400e000 { + compatible = "mediatek,mt7623-disp-mutex", + "mediatek,mt2701-disp-mutex"; + reg = <0 0x1400e000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_MUTEX_32K>; + }; + larb0: larb@14010000 { compatible = "mediatek,mt7623-smi-larb", "mediatek,mt2701-smi-larb"; @@ -744,6 +868,16 @@ power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; }; + rdma1: rdma@14012000 { + compatible = "mediatek,mt7623-disp-rdma", + "mediatek,mt2701-disp-rdma"; + reg = <0 0x14012000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>; + mediatek,larb = <&larb0>; + }; + imgsys: syscon@15000000 { compatible = "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", @@ -799,6 +933,34 @@ power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>; }; + dpi0: dpi@14014000 { + compatible = "mediatek,mt7623-dpi", + "mediatek,mt2701-dpi"; + reg = <0 0x14014000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DPI1_DIGL>, + <&mmsys CLK_MM_DPI1_ENGINE>, + <&topckgen CLK_TOP_TVDPLL>; + clock-names = "pixel", "engine", "pll"; + status = "disabled"; + }; + + hdmi0: hdmi@14015000 { + compatible = "mediatek,mt7623-hdmi", + "mediatek,mt8173-hdmi"; + reg = <0 0x14015000 0 0x400>; + clocks = <&mmsys CLK_MM_HDMI_PIXEL>, + <&mmsys CLK_MM_HDMI_PLL>, + <&mmsys CLK_MM_HDMI_AUDIO>, + <&mmsys CLK_MM_HDMI_SPDIF>; + clock-names = "pixel", "pll", "bclk", "spdif"; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + mediatek,syscon-hdmi = <&mmsys 0x900>; + cec = <&cec>; + status = "disabled"; + }; + hifsys: syscon@1a000000 { compatible = "mediatek,mt7623-hifsys", "mediatek,mt2701-hifsys", @@ -1071,6 +1233,21 @@ }; }; + hdmi_pins_a: hdmi-default { + pins-hdmi { + pinmux = ; + input-enable; + bias-pull-down; + }; + }; + + hdmi_ddc_pins_a: hdmi_ddc-default { + pins-hdmi-ddc { + pinmux = , + ; + }; + }; + i2c0_pins_a: i2c0-default { pins-i2c0 { pinmux = , diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts index 2b760f9..dbce86b 100644 --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts @@ -21,6 +21,19 @@ stdout-path = "serial2:115200n8"; }; + connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "d"; + ddc-i2c-bus = <&hdmiddc0>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi0_out>; + }; + }; + }; + cpus { cpu@0 { proc-supply = <&mt6323_vproc_reg>; @@ -114,10 +127,24 @@ }; }; +&bls { + status = "okay"; + + port { + bls_out: endpoint { + remote-endpoint = <&dpi0_in>; + }; + }; +}; + &btif { status = "okay"; }; +&cec { + status = "okay"; +}; + &cir { pinctrl-names = "default"; pinctrl-0 = <&cir_pins_a>; @@ -128,6 +155,26 @@ status = "okay"; }; +&dpi0 { + status = "okay"; + + ports { + port@0 { + reg = <0>; + dpi0_out: endpoint { + remote-endpoint = <&hdmi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpi0_in: endpoint { + remote-endpoint = <&bls_out>; + }; + }; + }; +}; + ð { status = "okay"; @@ -199,6 +246,42 @@ }; }; +&hdmi0 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins_a>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hdmi0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + + port@1 { + reg = <1>; + hdmi0_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; +}; + +&hdmiddc0 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_ddc_pins_a>; + status = "okay"; +}; + +&hdmi_phy { + mediatek,ibias = <0xa>; + mediatek,ibias_up = <0x1c>; + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; diff --git a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts index b760613..bdf9010 100644 --- a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts +++ b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts @@ -24,6 +24,19 @@ stdout-path = "serial2:115200n8"; }; + connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "d"; + ddc-i2c-bus = <&hdmiddc0>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi0_out>; + }; + }; + }; + cpus { cpu@0 { proc-supply = <&mt6323_vproc_reg>; @@ -106,10 +119,24 @@ }; }; +&bls { + status = "okay"; + + port { + bls_out: endpoint { + remote-endpoint = <&dpi0_in>; + }; + }; +}; + &btif { status = "okay"; }; +&cec { + status = "okay"; +}; + &cir { pinctrl-names = "default"; pinctrl-0 = <&cir_pins_a>; @@ -120,6 +147,26 @@ status = "okay"; }; +&dpi0 { + status = "okay"; + + ports { + port@0 { + reg = <0>; + dpi0_out: endpoint { + remote-endpoint = <&hdmi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpi0_in: endpoint { + remote-endpoint = <&bls_out>; + }; + }; + }; +}; + ð { status = "okay"; @@ -202,6 +249,42 @@ }; }; +&hdmi0 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins_a>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hdmi0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + + port@1 { + reg = <1>; + hdmi0_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; +}; + +&hdmiddc0 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_ddc_pins_a>; + status = "okay"; +}; + +&hdmi_phy { + mediatek,ibias = <0xa>; + mediatek,ibias_up = <0x1c>; + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; -- 1.9.1