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Mon, 26 Oct 2026 01:55:50 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6b44595d5e8sm3412794a12.6.2026.10.26.01.55.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 26 Oct 2026 01:55:49 -0700 (PDT) Message-ID: <0453a913-37d9-42cb-bb4a-511c112d21b4@oss.qualcomm.com> Date: Mon, 26 Oct 2026 09:55:46 +0100 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 01/10] drm/msm: serialise framebuffer pin state To: Dmitry Baryshkov , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Antonino Maniscalco , Kalyan Thota , Federico Amedeo Izzo , Helen Koike , Vignesh Raman , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20261024-fd-kms-fix-smmu-v5-0-a5b0b284aead@oss.qualcomm.com> <20261024-fd-kms-fix-smmu-v5-1-a5b0b284aead@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20261024-fd-kms-fix-smmu-v5-1-a5b0b284aead@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: fvFo-uClisc3NMKBnxmcrOhtJmTtD9e2 X-Authority-Analysis: v=2.4 cv=Ra0FmFtv c=1 sm=1 tr=0 ts=6adf1598 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=II6hZ13XIzipqfIPTBcA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDI2MDAzNSBTYWx0ZWRfX5IJ0Cjwrzm2S QCq1N7OuXTmCTx3fY80cJsOGi1AEUHUHyVZqoOsbUzN34Q9plTMnaRJto5HW9GGBzRBgsGG4vVw uKs82qtLQnRuru+98Lp7Tm30u7t5pdA= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDI2MDAzNSBTYWx0ZWRfXw8Y/jX03h7CE caNtjSqm3kwzhWHnyZJkLIaxG5nw5+2MyhrImaNBvtLwvmpMzG9vIMdkD/H+yZ59KdAXWghQhQD aFuCM6QND+L3pU8dRwQI6sqbXaVk1FnrzABQqCIcz7Vk6EjMyO+c3OovW8d9/0yC0BuQsnUGeRR zqQwthwQSGIrWS7k1kPA5ML/e+XM0Vulz9xZR1fawp7KS+fUbQSCJ9JjS50rqMMzkVd9LmCUPso 7JZcztvzaaTHu5t6Wx7eT+M+EEon/RVplZ2/D8SDLm0DslRoL/59/etG16ko5zslkeKUYduibQw MUmiCHnR2qzJk40dCdarvp/q5bS23ibTB+o3Yl0ir8lGzintG+iZsxkg4B724qskU7r7rRwQhgZ LOIuuAqa3IUNS7W8Z1UrA9qMOqBI4gMIgLUI0J5H4NMDj0qU/LmguV4d1YHAWipQnDxp/pV5V0T ALqYD0bc/PfXZIXpBSQ== X-Proofpoint-ORIG-GUID: fvFo-uClisc3NMKBnxmcrOhtJmTtD9e2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-26_01,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 impostorscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 malwarescore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610260035 On 10/24/26 1:25 AM, Dmitry Baryshkov wrote: > prepare_count, iova[] and the pins they describe are updated locklessly, > but drm_atomic_helper_commit() prepares a new state in parallel with the > completion of the previous one -- stall_checks() only stalls on the second > previous commit. Commit N+1's ->prepare_fb() thus runs while commit N is > in ->cleanup_fb(), and for a double-buffered flip that is the same > framebuffer: > > cleanup: prepare_count 1 -> 0 > prepare: prepare_count 0 -> 1, pins, stores iova[] > cleanup: memset(iova, 0) > > leaving the plane programmed with a NULL base address: > > arm-smmu 15000000.iommu: Unhandled context fault: fsr=0x402, > iova=0x00000100, fsynr=0x3e0023, cbfrsynra=0x1c00, cb=11 > > The opposite order is broken too since commit 8ac37c88f991 ("drm/msm: > Refcount framebuffer pins"): a prepare which finds the count non-zero > returns at once, assuming iova[] is populated. The clanker thinks this is correct and was able to reproduce by doing something similar with a test program It also left the following comment: The mutex approach in patch 1 has a direct precedent in omapdrm, so it's a sound choice. msm is unusual in caching iova[] per framebuffer and then zeroing it, which is why it needs the lock at all. If you want a fix with less state, the amdgpu approach of not clearing the cached address on cleanup would also avoid the NULL-base hazard. I'd keep the mutex, though, since patch 2's count-leak fix sits on top of it. any which way: Acked-by: Konrad Dybcio Konrad