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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2490658999fsm101472765ad.112.2025.09.01.05.38.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 01 Sep 2025 05:39:04 -0700 (PDT) Message-ID: <04549ce5-fa14-440d-b5b9-f8ff059f632a@oss.qualcomm.com> Date: Mon, 1 Sep 2025 20:38:56 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 02/14] dt-bindings: phy: Add QMP USB3+DP PHY for QCS615 To: Rob Herring Cc: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, fange.zhang@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, Bjorn Andersson , Konrad Dybcio , Dmitry Baryshkov References: <20250820-add-displayport-support-for-qcs615-platform-v3-0-a43bd25ec39c@oss.qualcomm.com> <20250820-add-displayport-support-for-qcs615-platform-v3-2-a43bd25ec39c@oss.qualcomm.com> <20250822142230.GA3591699-robh@kernel.org> From: Xiangxu Yin In-Reply-To: <20250822142230.GA3591699-robh@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: w_bf26nVQL7bD5uFd3bnVztJW7Kn-Knb X-Proofpoint-ORIG-GUID: w_bf26nVQL7bD5uFd3bnVztJW7Kn-Knb X-Authority-Analysis: v=2.4 cv=ccnSrmDM c=1 sm=1 tr=0 ts=68b593ea cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=mavVfetI76m9BAqSKQsA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODMwMDA0MiBTYWx0ZWRfX3ZWYiQok+a7N w4kVerMryXm1dwIRA6pYHJFBOJUNp7v0W4Te1LUUHtKmH1dR8P0jTJ8GGekDj0l26n6h8oVSpPO 9CROUx8DC92o9z0+UnznFaGne+A5xF14OVezIhZuuq0UeN9VoL2Zcgp6kceLBPVcvKUzdNaMGKY YILS9/U18WFiFFftzeAgvf2U8gELNXlkAVseZ52MVud9NgFRMS/14rTUuaR2bpMwflfVLfr3yZK EwItWfueeGT8nd2VY2mxx0ExT/f4u2sVQTv6c+q7YwX3Xw3F7r+T6SZN6+KbprFcUj7/bms2Eq/ pnw82cZYVJBpYDZYuJn0cXBn2wgX7PNb+7j3hvH/kQt6XO9+qZbSJwjcp0T7wKFDQptRN6jZECi aT8Nn4Ee X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-01_05,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 phishscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 clxscore=1015 suspectscore=0 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508300042 On 8/22/2025 10:22 PM, Rob Herring wrote: > On Wed, Aug 20, 2025 at 05:34:44PM +0800, Xiangxu Yin wrote: >> Add device tree binding documentation for the Qualcomm QMP USB3+DP PHY >> on QCS615 Platform. This PHY supports both USB3 and DP functionality >> over USB-C, with PHY mode switching capability. It does not support >> combo mode. >> >> Signed-off-by: Xiangxu Yin >> --- >> .../bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml | 108 +++++++++++++++++++++ >> 1 file changed, 108 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml >> new file mode 100644 >> index 0000000000000000000000000000000000000000..c2b1fbab2930f0653f4ddb95f7b54d8fe994f92d >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml >> @@ -0,0 +1,108 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/phy/qcom,qcs615-qmp-usb3dp-phy.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm QMP USB3-DP PHY controller (DP, QCS615) >> + >> +maintainers: >> + - Vinod Koul > No, this should be someone who has the h/w. I have discussed with Bjorn offline. In the next version, I’ll update myself as the maintainer for this dt-binding. >> + >> +description: >> + The QMP PHY controller supports physical layer functionality for both >> + USB3 and DisplayPort over USB-C. While it enables mode switching >> + between USB3 and DisplayPort, but does not support combo mode. > Wrap at 80 chars. Ok, will update next patch. >> + >> +properties: >> + compatible: >> + enum: >> + - qcom,qcs615-qmp-usb3-dp-phy >> + >> + reg: >> + maxItems: 1 >> + >> + clocks: >> + maxItems: 2 >> + >> + clock-names: >> + items: >> + - const: cfg_ahb >> + - const: ref >> + >> + resets: >> + maxItems: 2 >> + >> + reset-names: >> + items: >> + - const: phy_phy > phy_phy? > >> + - const: dp_phy >> + >> + vdda-phy-supply: true >> + >> + vdda-pll-supply: true >> + >> + "#clock-cells": >> + const: 1 >> + description: >> + See include/dt-bindings/phy/phy-qcom-qmp.h >> + >> + "#phy-cells": >> + const: 1 >> + description: >> + See include/dt-bindings/phy/phy-qcom-qmp.h >> + >> + qcom,tcsr-reg: >> + $ref: /schemas/types.yaml#/definitions/phandle-array >> + items: >> + - items: >> + - description: phandle to TCSR hardware block >> + - description: offset of the VLS CLAMP register >> + - items: >> + - description: phandle to TCSR hardware block >> + - description: offset of the DP PHY mode register >> + description: Clamp and PHY mode register present in the TCSR >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - clock-names >> + - resets >> + - reset-names >> + - vdda-phy-supply >> + - vdda-pll-supply >> + - "#clock-cells" >> + - "#phy-cells" >> + - qcom,tcsr-reg >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include >> + #include >> + >> + phy@88e8000 { >> + compatible = "qcom,qcs615-qmp-usb3-dp-phy"; >> + reg = <0x88e8000 0x2000>; >> + >> + clocks = <&gcc GCC_AHB2PHY_WEST_CLK>, >> + <&gcc GCC_USB3_SEC_CLKREF_CLK>; >> + clock-names = "cfg_ahb", >> + "ref"; >> + >> + resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR >, >> + <&gcc GCC_USB3_DP_PHY_SEC_BCR>; >> + reset-names = "phy_phy", >> + "dp_phy"; >> + >> + vdda-phy-supply = <&vreg_l11a>; >> + vdda-pll-supply = <&vreg_l5a>; >> + >> + #clock-cells = <1>; >> + #phy-cells = <1>; >> + >> + qcom,tcsr-reg = <&tcsr 0xbff0>, >> + <&tcsr 0xb24c>; >> + }; >> >> -- >> 2.34.1 >>