From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x226t/vorFVe3rZWweK5BCdWncVFNYQP0ZURh5mfbCv614EnTHiEuQ8ovuj88Qf38G4yqDMBs ARC-Seal: i=1; a=rsa-sha256; t=1516631602; cv=none; d=google.com; s=arc-20160816; b=OiuDTRKWS+vCn1/4EWyw+ftRE7Mv9IPY3nCB+UlLCHrjdLbQgP+HZ+Xc+J/nzxhkNZ 0534RB/vpAEHDDwwumV3+OMBUZmVtT3z+yhzX5MJaFW475GhMRj7po+KqAKrJ+j6Yq3T XPFBf8NE4Z/bHO5G7mRTrOiFNFZ0gQAwMnFuJKWMqFgOzG57Cxlm2MCK4EnAl1RKoWRA 2X18ftFcTMxz+Gpgnh/CQa82opyvljL/VBdxfh4Jk6FTfaXQ4M0M3upNebl1GPM7E49Y eJbaziQJ8c7mPEJeWGN+C4xIz7fFjf/dzqTIDOxhCuOSxYXRpxKmCZDIFXMsGaWcYiMA Z0zw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-language:content-transfer-encoding:in-reply-to:mime-version :user-agent:date:message-id:from:references:to:subject :arc-authentication-results; bh=hrQQrhp2rsHsIKWmrgbvPqmrvHsi1H8dwEPb7c7Wwhk=; b=kp1MNFr8LUAO9YDHEExP44kSVliaq+UR5DKgba+Z2J/rVB0YaCxZlUIWIhVyhoBTYk ksymyT4EVBQFE5QhirBYuGulah4skexTw+s1wO3Qd+4H+2TJdtoLFT+espbT/PAg9ELb I9Lk7/q7usqyOX+I8+ghiQm5Rr84XIUv3+GYqX1c+a3kWwjrGBd7UpgrBIKIJ/B3RYdL 7s7Pw+zVQRY/Zd66TN/Ox/6QUpMP6z0EcP7cR60WRgncEdnB9CneciM4iF7irUaKNR7X qQ71kYNznnuDCuaqzPAuEIV9PCTytgDHQhwm+1x0EYAWVHaRw1RmrL6lkqjaiH/oAQi+ ygyQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of prvs=553e45c5e=andrew.cooper3@citrix.com designates 185.25.65.24 as permitted sender) smtp.mailfrom=prvs=553e45c5e=Andrew.Cooper3@citrix.com Authentication-Results: mx.google.com; spf=pass (google.com: domain of prvs=553e45c5e=andrew.cooper3@citrix.com designates 185.25.65.24 as permitted sender) smtp.mailfrom=prvs=553e45c5e=Andrew.Cooper3@citrix.com X-IronPort-AV: E=Sophos;i="5.46,396,1511827200"; d="scan'208";a="66451288" Subject: Re: [PATCH v2 2/8] x86/cpufeatures: Add AMD feature bits for Prediction Command To: Tom Lendacky , David Woodhouse , , , , , , , , , , , , References: <1516528149-9370-1-git-send-email-dwmw@amazon.co.uk> <1516528149-9370-3-git-send-email-dwmw@amazon.co.uk> <568a0210-43a1-5580-c0f4-d6d8cc5e982a@amd.com> From: Andrew Cooper Message-ID: <046d1752-bf19-d80e-a7ce-cdf521bacf8c@citrix.com> Date: Mon, 22 Jan 2018 14:33:21 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.2 MIME-Version: 1.0 In-Reply-To: <568a0210-43a1-5580-c0f4-d6d8cc5e982a@amd.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Content-Language: en-GB X-ClientProxiedBy: AMSPEX02CAS02.citrite.net (10.69.22.113) To AMSPEX02CL02.citrite.net (10.69.22.126) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590195040636439803?= X-GMAIL-MSGID: =?utf-8?q?1590303499490788695?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: On 22/01/18 14:31, Tom Lendacky wrote: > On 1/21/2018 12:01 PM, Andrew Cooper wrote: >> On 21/01/18 17:50, Tom Lendacky wrote: >>> On 1/21/2018 3:49 AM, David Woodhouse wrote: >>>> AMD doesn't implement the Speculation Control MSR that Intel does, but >>>> the Prediction Control MSR does exist and is advertised by a separate >>>> CPUID bit. Add support for that. >>>> >>>> Signed-off-by: David Woodhouse >>>> --- >>>> arch/x86/include/asm/cpufeatures.h | 1 + >>>> arch/x86/kernel/cpu/scattered.c | 1 + >>>> 2 files changed, 2 insertions(+) >>>> >>>> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h >>>> index 2efb8d4..8c9e5c0 100644 >>>> --- a/arch/x86/include/asm/cpufeatures.h >>>> +++ b/arch/x86/include/asm/cpufeatures.h >>>> @@ -207,6 +207,7 @@ >>>> #define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* AMD Retpoline mitigation for Spectre variant 2 */ >>>> #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */ >>>> >>>> +#define X86_FEATURE_AMD_PRED_CMD ( 7*32+17) /* Prediction Command MSR (AMD) */ >>>> #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ >>>> #define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* Fill RSB on context switches */ >>>> >>>> diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c >>>> index df11f5d..4eb90b2 100644 >>>> --- a/arch/x86/kernel/cpu/scattered.c >>>> +++ b/arch/x86/kernel/cpu/scattered.c >>>> @@ -28,6 +28,7 @@ static const struct cpuid_bit cpuid_bits[] = { >>>> { X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 }, >>>> { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, >>>> { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, >>>> + { X86_FEATURE_AMD_PRED_CMD, CPUID_EBX, 12, 0x80000008, 0 }, >>> I replied to the previous version, but I'll add it here, too. >>> >>> This should be moved to the existing 0x80000008/EBX entry rather than have >>> it in scattered. >>> >>> Also, there will be a total of three bits: >>> IBPB: 0x80000008 EBX[12] >>> IBRS: 0x80000008 EBX[14] >>> STIBP: 0x80000008 EBX[15] >>> >>> Since IBRS and STIBP share the same MSR, if a processor only supports >>> STIBP (MSR bit 1), for ease of software implementation the processor >>> does not GP fault attempts to write bit 0. In a similar manner, if a >>> processor only suppors IBRS (MSR bit 0), the processor does not GP >>> fault attempts to write bit 1. >> Are you able to comment on the read behaviour after a write which is >> ignored? >> >> If the behaviour is "read as written" then virt cases are fine.  If the >> "ignore" causes a zero to be read back, then we're still going to need >> to intercept and emulate all VM accesses. > The behavior is "read as written", so the bit will be updated even though > the support for the bit is not present. Fantastic!  Thanks for confirming. ~Andrew