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From: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>
To: "Liang, Kan" <kan.liang@linux.intel.com>,
	Peter Zijlstra <peterz@infradead.org>,
	Ingo Molnar <mingo@redhat.com>,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Namhyung Kim <namhyung@kernel.org>,
	Ian Rogers <irogers@google.com>,
	Adrian Hunter <adrian.hunter@intel.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Andi Kleen <ak@linux.intel.com>,
	Eranian Stephane <eranian@google.com>
Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
	Dapeng Mi <dapeng1.mi@intel.com>
Subject: Re: [Patch v2 13/24] perf/x86/intel: Update dyn_constranit base on PEBS event precise level
Date: Wed, 5 Mar 2025 09:41:27 +0800	[thread overview]
Message-ID: <0496c7b0-098c-4b2f-9c71-a258a398c5a8@linux.intel.com> (raw)
In-Reply-To: <afdc5b07-9795-4049-8941-c2e3d2bbaa87@linux.intel.com>


On 2/27/2025 10:06 PM, Liang, Kan wrote:
>
> On 2025-02-18 10:28 a.m., Dapeng Mi wrote:
>> arch-PEBS provides CPUIDs to enumerate which counters support PEBS
>> sampling and precise distribution PEBS sampling. Thus PEBS constraints
>> should be dynamically configured base on these counter and precise
>> distribution bitmap instead of defining them statically.
>>
>> Update event dyn_constraint base on PEBS event precise level.
>>
>> Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
>> ---
>>  arch/x86/events/intel/core.c | 6 ++++++
>>  arch/x86/events/intel/ds.c   | 1 +
>>  2 files changed, 7 insertions(+)
>>
>> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
>> index 472366c3db22..c777e0531d40 100644
>> --- a/arch/x86/events/intel/core.c
>> +++ b/arch/x86/events/intel/core.c
>> @@ -4033,6 +4033,8 @@ static int intel_pmu_hw_config(struct perf_event *event)
>>  		return ret;
>>  
>>  	if (event->attr.precise_ip) {
>> +		struct arch_pebs_cap pebs_cap = hybrid(event->pmu, arch_pebs_cap);
>> +
>>  		if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT)
>>  			return -EINVAL;
>>  
>> @@ -4046,6 +4048,10 @@ static int intel_pmu_hw_config(struct perf_event *event)
>>  		}
>>  		if (x86_pmu.pebs_aliases)
>>  			x86_pmu.pebs_aliases(event);
>> +
>> +		if (x86_pmu.arch_pebs)
>> +			event->hw.dyn_constraint = event->attr.precise_ip >= 3 ?
>> +						   pebs_cap.pdists : pebs_cap.counters;
>>  	}
> The dyn_constraint is only required when the counter mask is different.
> I think the pebs_cap.counters should be very likely the same as the
> regular counter mask. Maybe something as below (not test).
>
> 	if (x86_pmu.arch_pebs) {
> 		u64 cntr_mask = event->attr.precise_ip >= 3 ?
> 				pebs_cap.pdists : pebs_cap.counters;
> 		if (cntr_mask != hybrid(event->pmu, intel_ctrl))
> 			event->hw.dyn_constraint = cntr_mask;
> 	}

Sure. Thanks.


>
> Thanks,
> Kan
>>  
>>  	if (needs_branch_stack(event)) {
>> diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
>> index 519767fc9180..615aefb4e52e 100644
>> --- a/arch/x86/events/intel/ds.c
>> +++ b/arch/x86/events/intel/ds.c
>> @@ -2948,6 +2948,7 @@ static void __init intel_arch_pebs_init(void)
>>  	x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
>>  	x86_pmu.drain_pebs = intel_pmu_drain_arch_pebs;
>>  	x86_pmu.pebs_capable = ~0ULL;
>> +	x86_pmu.flags |= PMU_FL_PEBS_ALL;
>>  
>>  	x86_pmu.pebs_enable = __intel_pmu_pebs_enable;
>>  	x86_pmu.pebs_disable = __intel_pmu_pebs_disable;
>

  reply	other threads:[~2025-03-05  1:41 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-18 15:27 [Patch v2 00/24] Arch-PEBS and PMU supports for Clearwater Forest and Panther Lake Dapeng Mi
2025-02-18 15:27 ` [Patch v2 01/24] perf/x86: Add dynamic constraint Dapeng Mi
2025-02-18 15:27 ` [Patch v2 02/24] perf/x86/intel: Add Panther Lake support Dapeng Mi
2025-02-18 15:27 ` [Patch v2 03/24] perf/x86/intel: Add PMU support for Clearwater Forest Dapeng Mi
2025-02-18 15:27 ` [Patch v2 04/24] perf/x86/intel: Parse CPUID archPerfmonExt leaves for non-hybrid CPUs Dapeng Mi
2025-02-18 15:27 ` [Patch v2 05/24] perf/x86/intel: Decouple BTS initialization from PEBS initialization Dapeng Mi
2025-02-18 15:28 ` [Patch v2 06/24] perf/x86/intel: Rename x86_pmu.pebs to x86_pmu.ds_pebs Dapeng Mi
2025-02-18 15:28 ` [Patch v2 07/24] perf/x86/intel: Introduce pairs of PEBS static calls Dapeng Mi
2025-02-18 15:28 ` [Patch v2 08/24] perf/x86/intel: Initialize architectural PEBS Dapeng Mi
2025-02-18 15:28 ` [Patch v2 09/24] perf/x86/intel/ds: Factor out common PEBS processing code to functions Dapeng Mi
2025-02-18 15:28 ` [Patch v2 10/24] perf/x86/intel: Process arch-PEBS records or record fragments Dapeng Mi
2025-02-25 10:39   ` Peter Zijlstra
2025-02-25 11:00     ` Peter Zijlstra
2025-02-26  5:20       ` Mi, Dapeng
2025-02-26  9:35         ` Peter Zijlstra
2025-02-26 15:45           ` Liang, Kan
2025-02-27  2:04             ` Mi, Dapeng
2025-02-25 20:42     ` Andi Kleen
2025-02-26  2:54     ` Mi, Dapeng
2025-02-18 15:28 ` [Patch v2 11/24] perf/x86/intel: Factor out common functions to process PEBS groups Dapeng Mi
2025-02-25 11:02   ` Peter Zijlstra
2025-02-26  5:24     ` Mi, Dapeng
2025-02-18 15:28 ` [Patch v2 12/24] perf/x86/intel: Allocate arch-PEBS buffer and initialize PEBS_BASE MSR Dapeng Mi
2025-02-25 11:18   ` Peter Zijlstra
2025-02-26  5:48     ` Mi, Dapeng
2025-02-26  9:46       ` Peter Zijlstra
2025-02-27  2:05         ` Mi, Dapeng
2025-02-25 11:25   ` Peter Zijlstra
2025-02-26  6:19     ` Mi, Dapeng
2025-02-26  9:48       ` Peter Zijlstra
2025-02-27  2:09         ` Mi, Dapeng
2025-02-18 15:28 ` [Patch v2 13/24] perf/x86/intel: Update dyn_constranit base on PEBS event precise level Dapeng Mi
2025-02-27 14:06   ` Liang, Kan
2025-03-05  1:41     ` Mi, Dapeng [this message]
2025-02-18 15:28 ` [Patch v2 14/24] perf/x86/intel: Setup PEBS data configuration and enable legacy groups Dapeng Mi
2025-02-18 15:28 ` [Patch v2 15/24] perf/x86/intel: Add SSP register support for arch-PEBS Dapeng Mi
2025-02-25 11:52   ` Peter Zijlstra
2025-02-26  6:56     ` Mi, Dapeng
2025-02-25 11:54   ` Peter Zijlstra
2025-02-25 20:44     ` Andi Kleen
2025-02-27  6:29       ` Mi, Dapeng
2025-02-18 15:28 ` [Patch v2 16/24] perf/x86/intel: Add counter group " Dapeng Mi
2025-02-18 15:28 ` [Patch v2 17/24] perf/core: Support to capture higher width vector registers Dapeng Mi
2025-02-25 20:32   ` Peter Zijlstra
2025-02-26  7:55     ` Mi, Dapeng
2025-02-18 15:28 ` [Patch v2 18/24] perf/x86/intel: Support arch-PEBS vector registers group capturing Dapeng Mi
2025-02-25 15:32   ` Peter Zijlstra
2025-02-26  8:08     ` Mi, Dapeng
2025-02-27  6:40       ` Mi, Dapeng
2025-03-04  3:08         ` Mi, Dapeng
2025-03-04 16:26           ` Liang, Kan
2025-03-05  1:34             ` Mi, Dapeng
2025-02-18 15:28 ` [Patch v2 19/24] perf tools: Support to show SSP register Dapeng Mi
2025-02-18 15:28 ` [Patch v2 20/24] perf tools: Enhance arch__intr/user_reg_mask() helpers Dapeng Mi
2025-02-18 15:28 ` [Patch v2 21/24] perf tools: Enhance sample_regs_user/intr to capture more registers Dapeng Mi
2025-02-18 15:28 ` [Patch v2 22/24] perf tools: Support to capture more vector registers (x86/Intel) Dapeng Mi
2025-02-18 15:28 ` [Patch v2 23/24] perf tools/tests: Add vector registers PEBS sampling test Dapeng Mi
2025-02-18 15:28 ` [Patch v2 24/24] perf tools: Fix incorrect --user-regs comments Dapeng Mi

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