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Mon, 28 Apr 2025 07:31:37 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 53S7Vb5J018597 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Apr 2025 07:31:37 GMT Received: from [10.239.133.49] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 28 Apr 2025 00:31:33 -0700 Message-ID: <04d46109-d499-4e91-88aa-4187145b811d@quicinc.com> Date: Mon, 28 Apr 2025 15:31:17 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 1/2] dt-bindings: arm: Add Qualcomm extended CTI To: Krzysztof Kozlowski , Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , References: <20240903121847.6964-1-quic_jinlmao@quicinc.com> <20240903121847.6964-2-quic_jinlmao@quicinc.com> <8d203417-e3da-4969-87ea-f77cdb720756@kernel.org> Content-Language: en-US From: Jinlong Mao In-Reply-To: <8d203417-e3da-4969-87ea-f77cdb720756@kernel.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: aDsDaYIgclR7eS8pnA0nbiEW7aeN6APZ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI4MDA2MiBTYWx0ZWRfX7EVVk9LNKvOj K0eTbT1JteIl+PlllryskKWOK8Jt+x2tQanwgSAcjyV2bqem670wEQhRF/vwWrof2G+PhU30bSk rPqSHsds4x9OFDalnlQCVRkYgWbNNV2Fd8Q923L8X86/7m6XJK11F7m+jDW9mmvNcvxaBcSX9wB qZPz7m4swNAwV3iMENhKSFNEvSQxYMnAbiJ/4CQUxPTWvlrx9C8COLmTeVf5WQf1NFnb5tQ7gm+ g2pp/Upsca3J1KAUuLwi1cMPwhqm9oyvLoovoHKkOkS7qjTXRmYu3ynbAi8jtqsLfYET4DQ6aaP JzHR9hENcQmv4WjQpI/3j3jcqMc0u4koQgH1C+VUvc5JKJhGKVwbYa26PiGQrAkIRWRbir1/D1m rb/VWxnXxVZ5jttiqT+CJdiCOzpJaXMT22JHqAXGhTk1JX6gGXndtatFG8iK8+B6ueRUg4v5 X-Authority-Analysis: v=2.4 cv=cfzSrmDM c=1 sm=1 tr=0 ts=680f2ed9 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=COk6AnOGAAAA:8 a=WjK4Y3n_-wVlLzch4jIA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: aDsDaYIgclR7eS8pnA0nbiEW7aeN6APZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-28_02,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 spamscore=0 mlxscore=0 mlxlogscore=999 adultscore=0 clxscore=1011 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504280062 On 2024/9/3 20:42, Krzysztof Kozlowski wrote: > On 03/09/2024 14:18, Mao Jinlong wrote: >> Add Qualcomm extended CTI support in CTI binding file. Qualcomm >> extended CTI supports up to 128 triggers. >> >> Signed-off-by: Mao Jinlong >> --- >> .../devicetree/bindings/arm/arm,coresight-cti.yaml | 14 ++++++++++++++ >> 1 file changed, 14 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml >> index 6a73eaa66a42..141efba7c697 100644 >> --- a/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml >> +++ b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml >> @@ -87,6 +87,10 @@ properties: >> - const: arm,coresight-cti-v8-arch >> - const: arm,coresight-cti >> - const: arm,primecell >> + - items: >> + - const: qcom,coresight-cti-extended > > That's just enum in previous entry/list. Sorry for the late response. This is a new CTI type. Need the three items in compatible at the same time, just like other kind of CTIs. > >> + - const: arm,coresight-cti >> + - const: arm,primecell >> >> reg: >> maxItems: 1 >> @@ -254,6 +258,16 @@ examples: >> clocks = <&soc_smc50mhz>; >> clock-names = "apb_pclk"; >> }; >> + # minimum extended CTI definition. >> + - | > > No need for new example. No differences here. This is a new type CTI. > > > Best regards, > Krzysztof >