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The amd64_edac module logs DIMM sizes on a > per-UMC per-CS granularity during init using these two registers. > > Currently, the module primarily considers only the Address Mask register > for computing DIMM sizes. The Secondary Address Mask register is only > considered for odd CS. Additionally, if it has been considered, the > Address Mask register is ignored altogether for that CS. For > power-of-two DIMMs i.e. DIMMs whose total capacity is a power of two > (32GB, 64GB, etc.), this is not an issue since only the Address Mask > register is used. > > For non-power-of-two DIMMs i.e, DIMMs whose total capacity is not a power > of two (48GB, 96GB, etc.), however, the Secondary Address Mask register > is used in conjunction with the Address Mask register. However, since the > module only considers either of the two registers for a CS, the size > computed by the module is incorrect. The Secondary Address Mask register > is not considered for even CS, and the Address Mask register is not > considered for odd CS. > > Introduce a new helper function so that both Address Mask and Secondary > Address Mask registers are considered, when valid, for computing DIMM > sizes. Furthermore, also rename some variables for greater clarity. > > Fixes: 81f5090db843 ("EDAC/amd64: Support asymmetric dual-rank DIMMs") > Reported-by: Žilvinas Žaltiena > Closes: https://lore.kernel.org/dbec22b6-00f2-498b-b70d-ab6f8a5ec87e@natrix.lt > Signed-off-by: Avadhut Naik > Tested-by: Žilvinas Žaltiena > Reviewed-by: Yazen Ghannam > Cc: stable@vger.kernel.org > --- > Changes in v2: > 1. Avoid unnecessary variable initialization. > 2. Modify commit message to accurately reflect the changes. > 3. Move check for non-zero Address Mask register into the new helper. > > Changes in v3: > 1. Add the missing Closes tag and rearrange tags per tip tree handbook. > 3. Slightly modify commit message to properly reflect the SOCs that may > encounter this issue. > 4. Rebase on top of edac-for-next. > > Changes in v4: > 1. Rebase on top of edac-for-next. > > Changes in v5: > 1. Change ordering of variable declarations to reverse fir tree. > 2. Explicitly state what power-of-two and non-power-of-two DIMMs are in > the commit message and ensure that the changelog is ignored by patch > handling tools. > 3. Rebase on top of edac-for-next. > > Links: > v1: https://lore.kernel.org/all/20250327210718.1640762-1-avadhut.naik@amd.com/ > v2: https://lore.kernel.org/all/20250415213150.755255-1-avadhut.naik@amd.com/ > v3: https://lore.kernel.org/all/20250416222552.1686475-1-avadhut.naik@amd.com/ > v4: https://lore.kernel.org/all/20250513192221.784445-1-avadhut.naik@amd.com/ > --- > drivers/edac/amd64_edac.c | 57 ++++++++++++++++++++++++--------------- > 1 file changed, 36 insertions(+), 21 deletions(-) > > diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c > index 90f0eb7cc5b9..35e59abef598 100644 > --- a/drivers/edac/amd64_edac.c > +++ b/drivers/edac/amd64_edac.c > @@ -1209,7 +1209,9 @@ static int umc_get_cs_mode(int dimm, u8 ctrl, struct amd64_pvt *pvt) > if (csrow_enabled(2 * dimm + 1, ctrl, pvt)) > cs_mode |= CS_ODD_PRIMARY; > > - /* Asymmetric dual-rank DIMM support. */ > + if (csrow_sec_enabled(2 * dimm, ctrl, pvt)) > + cs_mode |= CS_EVEN_SECONDARY; > + > if (csrow_sec_enabled(2 * dimm + 1, ctrl, pvt)) > cs_mode |= CS_ODD_SECONDARY; > > @@ -1230,12 +1232,13 @@ static int umc_get_cs_mode(int dimm, u8 ctrl, struct amd64_pvt *pvt) > return cs_mode; > } > > -static int __addr_mask_to_cs_size(u32 addr_mask_orig, unsigned int cs_mode, > - int csrow_nr, int dimm) > +static int calculate_cs_size(u32 mask, unsigned int cs_mode) > { > - u32 msb, weight, num_zero_bits; > - u32 addr_mask_deinterleaved; > - int size = 0; > + int msb, weight, num_zero_bits; > + u32 deinterleaved_mask; > + > + if (!mask) > + return 0; > > /* > * The number of zero bits in the mask is equal to the number of bits > @@ -1248,19 +1251,30 @@ static int __addr_mask_to_cs_size(u32 addr_mask_orig, unsigned int cs_mode, > * without swapping with the most significant bit. This can be handled > * by keeping the MSB where it is and ignoring the single zero bit. > */ > - msb = fls(addr_mask_orig) - 1; > - weight = hweight_long(addr_mask_orig); > + msb = fls(mask) - 1; > + weight = hweight_long(mask); > num_zero_bits = msb - weight - !!(cs_mode & CS_3R_INTERLEAVE); > > /* Take the number of zero bits off from the top of the mask. */ > - addr_mask_deinterleaved = GENMASK_ULL(msb - num_zero_bits, 1); > + deinterleaved_mask = GENMASK(msb - num_zero_bits, 1); > + edac_dbg(1, " Deinterleaved AddrMask: 0x%x\n", deinterleaved_mask); > + > + return (deinterleaved_mask >> 2) + 1; > +} > + > +static int __addr_mask_to_cs_size(u32 addr_mask, u32 addr_mask_sec, > + unsigned int cs_mode, int csrow_nr, int dimm) > +{ > + int size; > > edac_dbg(1, "CS%d DIMM%d AddrMasks:\n", csrow_nr, dimm); > - edac_dbg(1, " Original AddrMask: 0x%x\n", addr_mask_orig); > - edac_dbg(1, " Deinterleaved AddrMask: 0x%x\n", addr_mask_deinterleaved); > + edac_dbg(1, " Primary AddrMask: 0x%x\n", addr_mask); > > /* Register [31:1] = Address [39:9]. Size is in kBs here. */ > - size = (addr_mask_deinterleaved >> 2) + 1; > + size = calculate_cs_size(addr_mask, cs_mode); > + > + edac_dbg(1, " Secondary AddrMask: 0x%x\n", addr_mask_sec); > + size += calculate_cs_size(addr_mask_sec, cs_mode); > > /* Return size in MBs. */ > return size >> 10; > @@ -1269,8 +1283,8 @@ static int __addr_mask_to_cs_size(u32 addr_mask_orig, unsigned int cs_mode, > static int umc_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc, > unsigned int cs_mode, int csrow_nr) > { > + u32 addr_mask = 0, addr_mask_sec = 0; > int cs_mask_nr = csrow_nr; > - u32 addr_mask_orig; > int dimm, size = 0; > > /* No Chip Selects are enabled. */ > @@ -1308,13 +1322,13 @@ static int umc_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc, > if (!pvt->flags.zn_regs_v2) > cs_mask_nr >>= 1; > > - /* Asymmetric dual-rank DIMM support. */ > - if ((csrow_nr & 1) && (cs_mode & CS_ODD_SECONDARY)) > - addr_mask_orig = pvt->csels[umc].csmasks_sec[cs_mask_nr]; > - else > - addr_mask_orig = pvt->csels[umc].csmasks[cs_mask_nr]; > + if (cs_mode & (CS_EVEN_PRIMARY | CS_ODD_PRIMARY)) > + addr_mask = pvt->csels[umc].csmasks[cs_mask_nr]; > + > + if (cs_mode & (CS_EVEN_SECONDARY | CS_ODD_SECONDARY)) > + addr_mask_sec = pvt->csels[umc].csmasks_sec[cs_mask_nr]; > > - return __addr_mask_to_cs_size(addr_mask_orig, cs_mode, csrow_nr, dimm); > + return __addr_mask_to_cs_size(addr_mask, addr_mask_sec, cs_mode, csrow_nr, dimm); > } > > static void umc_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl) > @@ -3512,9 +3526,10 @@ static void gpu_get_err_info(struct mce *m, struct err_info *err) > static int gpu_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc, > unsigned int cs_mode, int csrow_nr) > { > - u32 addr_mask_orig = pvt->csels[umc].csmasks[csrow_nr]; > + u32 addr_mask = pvt->csels[umc].csmasks[csrow_nr]; > + u32 addr_mask_sec = pvt->csels[umc].csmasks_sec[csrow_nr]; > > - return __addr_mask_to_cs_size(addr_mask_orig, cs_mode, csrow_nr, csrow_nr >> 1); > + return __addr_mask_to_cs_size(addr_mask, addr_mask_sec, cs_mode, csrow_nr, csrow_nr >> 1); > } > > static void gpu_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl) > > base-commit: 855b5de2e562c07d6cda4deb08d09dc2e0e2b18d Any further feedback on this? -- Thanks, Avadhut Naik