From: Hal Feng <hal.feng@starfivetech.com>
To: Conor Dooley <conor.dooley@microchip.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-riscv@lists.infradead.org>,
Stephen Boyd <sboyd@kernel.org>,
"Michael Turquette" <mturquette@baylibre.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor@kernel.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Ben Dooks <ben.dooks@sifive.com>,
"Daniel Lezcano" <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>,
Emil Renner Berthing <emil.renner.berthing@canonical.com>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v4 09/19] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator
Date: Thu, 23 Feb 2023 18:22:52 +0800 [thread overview]
Message-ID: <04e071d8-3195-d065-d33f-ef81e3fcfb22@starfivetech.com> (raw)
In-Reply-To: <Y/XxOw+T0WdYY7jP@wendy>
On Wed, 22 Feb 2023 10:40:59 +0000, Conor Dooley wrote:
> On Wed, Feb 22, 2023 at 10:13:19AM +0100, Krzysztof Kozlowski wrote:
>> On 21/02/2023 03:46, Hal Feng wrote:
>> > From: Emil Renner Berthing <kernel@esmil.dk>
>> >
>> > Add bindings for the system clock and reset generator (SYSCRG) on the
>> > JH7110 RISC-V SoC by StarFive Ltd.
>> >
>> > Reviewed-by: Rob Herring <robh@kernel.org>
>> > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
>> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>>
>> I don't know what is happening here as neither this nor other patchset
>> explains anything. Please stop writing what you do in the patches, but
>> explain why. What is easy to get.
>>
>> (...)
>>
>>
>> > +
>> > +#define JH7110_SYSCLK_PLL0_OUT 190
>> > +#define JH7110_SYSCLK_PLL1_OUT 191
>> > +#define JH7110_SYSCLK_PLL2_OUT 192
>>
>> NAK. Do not add incorrect bindings just to remove it THE SAME TIME.
>
> For some context, the PLL driver series [1] does the following, which is
> where this complaint stems from:
>> diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h
>> index 5e4f21ca0642..086a6ddcf380 100644
>> --- a/include/dt-bindings/clock/starfive,jh7110-crg.h
>> +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
>> @@ -6,6 +6,12 @@
>> #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
>> #define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
>>
>> +/* PLL clocks */
>> +#define JH7110_CLK_PLL0_OUT 0
>> +#define JH7110_CLK_PLL1_OUT 1
>> +#define JH7110_CLK_PLL2_OUT 2
>> +#define JH7110_PLLCLK_END 3
>> +
>> /* SYSCRG clocks */
>> #define JH7110_SYSCLK_CPU_ROOT 0
>> #define JH7110_SYSCLK_CPU_CORE 1
>> @@ -198,11 +204,7 @@
>> #define JH7110_SYSCLK_TDM_TDM_INV 188
>> #define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189
>>
>> -#define JH7110_SYSCLK_PLL0_OUT 190
>> -#define JH7110_SYSCLK_PLL1_OUT 191
>> -#define JH7110_SYSCLK_PLL2_OUT 192
>
> I was talking to Emil, who pointed out that these defines aren't
> actually ever used in the dts, so there's nothing really gained
> by adding them here in the first place.
> Seems like this series could simply move these defines into the driver
> (as the PLL addition series also does) and then we would not have to
> be worried about breaking the ABI in the future?
Sorry for that I didn't synchronize this with Xingyu. I'll move these
PLL definitions into the driver in the next version.
Best regards,
Hal
>
> 1 - https://patchwork.kernel.org/project/linux-riscv/patch/20230221141147.303642-3-xingyu.wu@starfivetech.com/
>
next prev parent reply other threads:[~2023-02-23 10:23 UTC|newest]
Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-21 2:46 [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
2023-02-21 2:46 ` [PATCH v4 01/19] clk: starfive: Factor out common JH7100 and JH7110 code Hal Feng
2023-02-21 2:46 ` [PATCH v4 02/19] clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h Hal Feng
2023-02-21 2:46 ` [PATCH v4 03/19] clk: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng
2023-02-21 2:46 ` [PATCH v4 04/19] reset: Create subdirectory for StarFive drivers Hal Feng
2023-02-21 2:46 ` [PATCH v4 05/19] reset: starfive: Factor out common JH71X0 reset code Hal Feng
2023-02-21 17:10 ` Conor Dooley
2023-02-21 2:46 ` [PATCH v4 06/19] reset: starfive: Extract the " Hal Feng
2023-02-21 17:13 ` Conor Dooley
2023-02-21 2:46 ` [PATCH v4 07/19] reset: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng
2023-02-21 17:17 ` Conor Dooley
2023-02-21 2:46 ` [PATCH v4 08/19] reset: starfive: jh71x0: Use 32bit I/O on 32bit registers Hal Feng
2023-02-21 2:46 ` [PATCH v4 09/19] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator Hal Feng
2023-02-21 17:23 ` Conor Dooley
2023-02-23 3:40 ` Hal Feng
2023-02-22 9:13 ` Krzysztof Kozlowski
2023-02-22 10:40 ` Conor Dooley
2023-02-23 10:22 ` Hal Feng [this message]
2023-02-21 2:46 ` [PATCH v4 10/19] dt-bindings: clock: Add StarFive JH7110 always-on " Hal Feng
2023-02-21 17:26 ` Conor Dooley
2023-02-23 5:52 ` Hal Feng
2023-03-09 14:22 ` Geert Uytterhoeven
2023-03-13 2:29 ` Hal Feng
2023-02-21 2:46 ` [PATCH v4 11/19] clk: starfive: Add StarFive JH7110 system clock driver Hal Feng
2023-02-21 15:12 ` Conor Dooley
2023-02-23 6:17 ` Hal Feng
2023-02-26 16:07 ` Emil Renner Berthing
2023-02-28 2:30 ` Hal Feng
2023-02-21 2:46 ` [PATCH v4 12/19] clk: starfive: Add StarFive JH7110 always-on " Hal Feng
2023-02-26 17:34 ` Emil Renner Berthing
2023-02-28 2:42 ` Hal Feng
2023-03-09 9:43 ` Hal Feng
2023-03-09 14:06 ` Emil Renner Berthing
2023-03-09 18:11 ` Conor Dooley
2023-03-09 18:19 ` Emil Renner Berthing
2023-03-09 19:32 ` Palmer Dabbelt
2023-02-21 2:46 ` [PATCH v4 13/19] reset: starfive: Add StarFive JH7110 reset driver Hal Feng
2023-02-21 15:33 ` Emil Renner Berthing
2023-02-21 16:34 ` Conor Dooley
2023-02-23 6:48 ` Hal Feng
2023-02-23 6:29 ` Hal Feng
2023-02-21 2:46 ` [PATCH v4 14/19] dt-bindings: timer: Add StarFive JH7110 clint Hal Feng
2023-02-21 2:46 ` [PATCH v4 15/19] dt-bindings: interrupt-controller: Add StarFive JH7110 plic Hal Feng
2023-02-21 2:46 ` [PATCH v4 16/19] dt-bindings: riscv: Add SiFive S7 compatible Hal Feng
2023-02-21 11:38 ` Krzysztof Kozlowski
2023-02-21 15:10 ` Conor Dooley
2023-02-21 2:46 ` [PATCH v4 17/19] riscv: dts: starfive: Add initial StarFive JH7110 device tree Hal Feng
2023-02-21 17:03 ` Conor Dooley
2023-02-23 7:16 ` Hal Feng
2023-02-27 18:10 ` Conor Dooley
2023-02-21 2:46 ` [PATCH v4 18/19] riscv: dts: starfive: Add StarFive JH7110 pin function definitions Hal Feng
2023-02-21 2:46 ` [PATCH v4 19/19] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree Hal Feng
2023-02-21 15:03 ` Emil Renner Berthing
2023-02-23 8:50 ` Hal Feng
2023-02-27 18:12 ` Conor Dooley
2023-02-27 20:00 ` Conor Dooley
2023-02-28 2:58 ` Hal Feng
2023-02-22 15:00 ` [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC patchwork-bot+linux-riscv
2023-03-03 19:08 ` Tommaso Merciai
2023-03-06 3:29 ` Hal Feng
2023-03-06 10:22 ` Tommaso Merciai
2023-03-07 8:36 ` Hal Feng
2023-03-07 8:51 ` Conor Dooley
2023-03-07 10:08 ` Hal Feng
2023-03-08 12:28 ` Tommaso Merciai
2023-03-08 13:36 ` Conor Dooley
2023-03-09 16:49 ` Tommaso Merciai
2023-03-09 17:52 ` Conor Dooley
2023-03-09 18:58 ` Tommaso Merciai
2023-03-09 19:03 ` Conor Dooley
2023-03-10 7:48 ` Tommaso Merciai
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=04e071d8-3195-d065-d33f-ef81e3fcfb22@starfivetech.com \
--to=hal.feng@starfivetech.com \
--cc=aou@eecs.berkeley.edu \
--cc=ben.dooks@sifive.com \
--cc=conor.dooley@microchip.com \
--cc=conor@kernel.org \
--cc=daniel.lezcano@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=emil.renner.berthing@canonical.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=krzysztof.kozlowski@linaro.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=maz@kernel.org \
--cc=mturquette@baylibre.com \
--cc=p.zabel@pengutronix.de \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=robh+dt@kernel.org \
--cc=sboyd@kernel.org \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
Powered by JetHome