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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa6ab44e881sm419566066b.26.2024.12.13.05.08.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 13 Dec 2024 05:08:51 -0800 (PST) Message-ID: <04e489be-231a-43b8-a701-1173ea744bae@oss.qualcomm.com> Date: Fri, 13 Dec 2024 14:08:48 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] arm64: dts: qcom: x1e80100-crd: Add USB multiport fingerprint readery To: Stephan Gerhold , Krishna Kurapati Cc: Johan Hovold , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Abel Vesa , Krishna Kurapati , Thinh Nguyen , linux-usb@vger.kernel.org References: <20241118-x1e80100-crd-fp-v1-0-ec6b553a2e53@linaro.org> <20241118-x1e80100-crd-fp-v1-1-ec6b553a2e53@linaro.org> <41106fd7-5348-4d21-9ae7-8466f5634b4c@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: Lpont4eLmYJ9r4U8Aeh3Zvz7HPrySVCe X-Proofpoint-GUID: Lpont4eLmYJ9r4U8Aeh3Zvz7HPrySVCe X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 priorityscore=1501 spamscore=0 mlxlogscore=999 impostorscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412130092 On 3.12.2024 5:05 PM, Stephan Gerhold wrote: > On Tue, Dec 03, 2024 at 09:07:22PM +0530, Krishna Kurapati wrote: >> On 12/3/2024 5:00 PM, Stephan Gerhold wrote: >>> On Tue, Dec 03, 2024 at 11:20:48AM +0100, Johan Hovold wrote: >>>> [ +CC: Krishna, Thinh and the USB list ] >>>> >>>> On Mon, Nov 18, 2024 at 11:34:29AM +0100, Stephan Gerhold wrote: >>>>> The X1E80100 CRD has a Goodix fingerprint reader connected to the USB >>>>> multiport controller on eUSB6. All other ports (including USB super-speed >>>>> pins) are unused. >>>>> >>>>> Set it up in the device tree together with the NXP PTN3222 repeater. >>>>> >>>>> Signed-off-by: Stephan Gerhold >>>>> --- >>>>> arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 48 +++++++++++++++++++++++++++++++ >>>>> 1 file changed, 48 insertions(+) >>>>> >>>>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts >>>>> index 39f9d9cdc10d..44942931c18f 100644 >>>>> --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts >>>>> +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts >>>>> @@ -735,6 +735,26 @@ keyboard@3a { >>>>> [...] >>>>> @@ -1260,3 +1288,23 @@ &usb_1_ss2_dwc3_hs { >>>>> &usb_1_ss2_qmpphy_out { >>>>> remote-endpoint = <&pmic_glink_ss2_ss_in>; >>>>> }; >>>>> + >>>>> +&usb_mp { >>>>> + status = "okay"; >>>>> +}; >>>>> + >>>>> +&usb_mp_dwc3 { >>>>> + /* Limit to USB 2.0 and single port */ >>>>> + maximum-speed = "high-speed"; >>>>> + phys = <&usb_mp_hsphy1>; >>>>> + phy-names = "usb2-1"; >>>>> +}; >>>> >>>> The dwc3 driver determines (and acts on) the number of ports based on >>>> the port interrupts in DT and controller capabilities. >>>> >>>> I'm not sure we can (should) just drop the other HS PHY and the SS PHYs >>>> that would still be there in the SoC (possibly initialised by the boot >>>> firmware). >>>> >>>> I had a local patch to enable the multiport controller (for the suspend >>>> work) and I realise that you'd currently need to specify a repeater also >>>> for the HS PHY which does not have one, but that should be possible to >>>> fix somehow. >>>> >>> >>> I think there are two separate questions here: >>> >>> 1. Should we (or do we even need to) enable unused PHYs? >>> 2. Do we need to power off unused PHYs left enabled by the firmware? >>> >>> For (1), I'm not not sure if there is a technical reason that requires >>> us to. And given that PHYs typically consume quite a bit of power, I'm >>> not sure if we should. Perhaps it's not worth spending effort on this >>> minor optimization now, but then the device tree would ideally still >>> tell us which PHYs are actually used (for future optimizations). >>> >>> For (2), yes, we probably need to. But my impression so far is that this >>> might be a larger problem that we need to handle on the SoC level. I >>> have seen some firmware versions that blindly power up all USB >>> controllers, even completely unused ones. Ideally we would power down >>> unused components during startup and then leave them off. >>> >> >> This question might be a dumb one, if so please ignore it. >> >> But if we skip adding unused phys in DTS node, the core driver wouldn't have >> access to all phys and we wouldn't be able to get references to unused ones >> (un-mentioned ones in DTS). So how can we power them off from core driver if >> we don't have reference to them ? >> > > The question is not dumb at all, it's a very valid one. :-) > > Perhaps it's easier if we keep them all listed on the USB controllers > and have something else to mark them as unused. The downside of that > option is that we might not be able to have a complete description of > the PHY with all resources. For example on the CRD there is no eUSB > repeater we could model for the first USB port (usb2-0), but it's needed > to enable the qcom,x1e80100-snps-eusb2-phy. So we have the choice between a silent failure or a loud non-failure wrt acquiring the repeater.. not sure which one is better Konrad