From: Dan Magenheimer <dan.magenheimer@oracle.com>
To: dan.magenheimer@oracle.com,
Venkatesh Pallipadi <venki@google.com>,
Len Brown <lenb@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>, linux-kernel@vger.kernel.org
Subject: RE: tsc reliability for Intel Core 2 Duo "Conroe"
Date: Thu, 27 May 2010 09:26:13 -0700 (PDT) [thread overview]
Message-ID: <04f8be9a-78ea-45fc-9a6f-c788ca10ea69@default> (raw)
In-Reply-To: <a20d4b76-5ba0-44cf-a26b-f58129377354@default>
> After digging deeper, it appears that this processor is entering
> C2 (as can be seen /sys/devices/system/cpu/cpu*/cpuidle/ output below)
> despite the documentation I have, as well as this posting from Len:
> http://forum.soft32.com/linux/ACPI-states-Conroe-ftopict339089.html
> I wonder if C1E state is somehow incorrectly getting recorded as
> C2 state? Or maybe TSC doesn't stop in C2 (TSC is most certainly
> not stopping), in which case the test in tsc_check_state() should
> be againt ACPI_STATE_C2?
>
> In any case, this appears to now be an ACPI C-state question
> so thanks, Venki, for cc'ing Len... and tglx is off the hook :-)
>
> Len, note that this box is an Intel SDP so if it is an odd
> duck, please just let me know... though I think I may have
> some Xen code to fix depending on the answer to the above.
Never mind... it appears this box has a BIOS setting to enable/disable
C2 that I didn't find in the documentation. With C2 disabled,
TSC is properly selected as the clocksource.
Sorry for the noise.
prev parent reply other threads:[~2010-05-27 16:27 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-05-26 17:41 Dan Magenheimer
2010-05-26 22:21 ` Venkatesh Pallipadi
2010-05-26 23:26 ` Dan Magenheimer
2010-05-27 16:26 ` Dan Magenheimer [this message]
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