From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-m155105.qiye.163.com (mail-m155105.qiye.163.com [101.71.155.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7AD02304BDC; Fri, 13 Mar 2026 03:25:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=101.71.155.105 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773372335; cv=none; b=Z0G0IYW7qABDJLT8DrhmQCWe52h9aQOvscdwko80L/WoQueLNU1htlLwFdi6Rcqj1nGbI6n2TOct0m5iHhPR+l9UBPsMk9mlcqqPSesr4X62CS79l8Trhzy7TuZKVZ+h07xRHasTPuYBV6pFH5R+MKCPfkv2j0RW0x0D0IiuzPo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773372335; c=relaxed/simple; bh=7IroXPo25acpPgw/E5upv97HBXA+EjYkyKQvzU7Uoh0=; h=Cc:Subject:To:References:From:Message-ID:Date:MIME-Version: In-Reply-To:Content-Type; b=oWH8wxKCcF/QNesTK3W2vC76mOS10+E63DEE0eYZuQfDglhVukTxE8OzWg2+E5AQxfPRZ2aIivAOhZCUhFveAlKtWROXx76k8jWpmOtNRWRul/jpkZwYY/7TkdiwmihOIsHsTDqLhZnumxlU1HjvSpnHA2y426KKRuHCnZGCyJ8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=LM6+Tvo2; arc=none smtp.client-ip=101.71.155.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="LM6+Tvo2" Received: from [192.168.61.151] (unknown [110.83.51.2]) by smtp.qiye.163.com (Hmail) with ESMTP id 36c931471; Fri, 13 Mar 2026 10:49:56 +0800 (GMT+08:00) Cc: shawn.lin@rock-chips.com, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, mayank.rana@oss.qualcomm.com, quic_vbadigan@quicinc.com Subject: Re: [PATCH v3 3/3] PCI: qcom: Program T_POWER_ON To: Krishna Chaitanya Chundru , Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Rob Herring , Bjorn Helgaas , Jingoo Han References: <20260311-t_power_on_fux-v3-0-9b1f1d09c6f3@oss.qualcomm.com> <20260311-t_power_on_fux-v3-3-9b1f1d09c6f3@oss.qualcomm.com> From: Shawn Lin Message-ID: <04fdfe0b-5867-0a94-75ec-44cec913756d@rock-chips.com> Date: Fri, 13 Mar 2026 10:49:56 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In-Reply-To: <20260311-t_power_on_fux-v3-3-9b1f1d09c6f3@oss.qualcomm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-HM-Tid: 0a9ce519c35809cckunmfe456f736a738 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlDGUkdVkwdGk9PTB8fQhgYS1YVFAkWGhdVEwETFh oSFyQUDg9ZV1kYEgtZQVlKSktVQ0hVTkpVSVlXWRYaDxIVHRRZQVlPS0hVSktJT09PSFVKS0tVSk JLS1kG DKIM-Signature: a=rsa-sha256; b=LM6+Tvo2c2bxR7lHJdkU5WhYkmEWZ5aaEQhLXrt88R54BmcnsYg+swaLmqJ9HWzChGGiS+RjWzh7v9CSgrFc7ljXbVaOgZqHgq8M5p3MXRrmSxFfHS+DcgvPjblZ553/bu7uNKgbIKWXUPSt37zHIZiRFYYluEAWccjprnvyUHA=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=XcX4EUH+vO15CDcdQiC0rQ1HswKB0uSszqiEkuDD5i0=; h=date:mime-version:subject:message-id:from; 在 2026/03/11 星期三 20:40, Krishna Chaitanya Chundru 写道: > Some platforms have incorrect T_POWER_ON value programmed in hardware. > Generally these will be corrected by bootloaders, but not all targets > support bootloaders to program correct values due to that > LTR_L1.2_THRESHOLD value calculated by aspm driver can be wrong, which > can result in improper L1.2 exit behavior and if AER happens to be > supported and enabled, the error may be *reported* via AER. > > Parse "t-power-on-us" property from each root port node and program them > as part of host initialization using dw_pcie_program_t_power_on() before > link training. > > This property in added to the dtschema here[1]. > > Signed-off-by: Krishna Chaitanya Chundru > Link[1]: https://lore.kernel.org/all/20260205093346.667898-1-krishna.chundru@oss.qualcomm.com/ > --- > drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 67a16af69ddc75fca1b123e70715e692a91a9135..63d5628e988d3c07f42099c0d86e6b80fd54ce32 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -269,6 +269,7 @@ struct qcom_pcie_perst { > struct qcom_pcie_port { > struct list_head list; > struct phy *phy; > + u32 l1ss_t_power_on; u16? > struct list_head perst; > }; > > @@ -1283,6 +1284,14 @@ static int qcom_pcie_phy_power_on(struct qcom_pcie *pcie) > return 0; > } > > +static void qcom_pcie_configure_ports(struct qcom_pcie *pcie) > +{ > + struct qcom_pcie_port *port; > + > + list_for_each_entry(port, &pcie->ports, list) > + dw_pcie_program_t_power_on(pcie->pci, port->l1ss_t_power_on); > +} > + > static int qcom_pcie_host_init(struct dw_pcie_rp *pp) > { > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > @@ -1317,6 +1326,8 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) > dw_pcie_remove_capability(pcie->pci, PCI_CAP_ID_MSIX); > dw_pcie_remove_ext_capability(pcie->pci, PCI_EXT_CAP_ID_DPC); > > + qcom_pcie_configure_ports(pcie); > + > qcom_pcie_perst_deassert(pcie); > > if (pcie->cfg->ops->config_sid) { > @@ -1759,6 +1770,8 @@ static int qcom_pcie_parse_port(struct qcom_pcie *pcie, struct device_node *node > if (ret) > return ret; > > + of_property_read_u32(node, "t-power-on-us", &port->l1ss_t_power_on); Ditto? > + > port->phy = phy; > INIT_LIST_HEAD(&port->list); > list_add_tail(&port->list, &pcie->ports); >