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charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI5MDA3OSBTYWx0ZWRfX82/ciHmyNqWC Zhf+bhWt4mFdlURZKpNgEty8EL7uHyiQPYFEuJHczvJ8jvF4JmNuG3Ypx8thakD1Vs2dEYGiXSu 9SijCXbk3gMwe0GvHl3vIl3w4t5RaxA= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI5MDA3OSBTYWx0ZWRfX3gLtZW2wSoj5 yBgWOM1+vbpmgMan6QkW7CraEBNz+P9mBo68woIzszVmtT238Wp0i/0ixAVNxj80DYxCKxovj6c OWhycpScsIyw4nOhNLoHVIeHp+nnu7683vDkZmG8pZFgsW6EwPUwfbJe0c5vyx12EEYL21nctie Ilzy3DVFAnM2n8Gjo2LP3+MuSQ7qdsKKFGmLxWwVHvpdDCGcdXihg8CmKhVDLifeff0wbJxW7Y4 S4DBPvWIbq+OkEoQS6cS/KwV7WXQpiK+roHQG88z673+pYnkEmtyOyri0pM9JlLXqbYziCD6gmD Hds8jC29YECFAcMpLQmq608sikEHStueL2BLo3C7MYBIGKyp1CcCEazS06K7TkXZRaPdHRy4l5j yLz/goI51zbM8en0alTh0ydrV5VlcvPhnTkxepdfbxn9GSlhqJMvtIw8qpBeoh4oeHzJmCemf/j Subz2exsU1kMz7Kfc2g== X-Proofpoint-GUID: VsvNb-VHtjmDIoCGEoK91pC-kB-C5NEF X-Authority-Analysis: v=2.4 cv=cefiaHDM c=1 sm=1 tr=0 ts=6a42400f cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=6UAb0L3E1jN75_jUm_YA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-ORIG-GUID: VsvNb-VHtjmDIoCGEoK91pC-kB-C5NEF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-29_02,2026-06-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 adultscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606290079 On 6/29/26 8:43 AM, Imran Shaik wrote: > > > On 25-06-2026 02:14 pm, Konrad Dybcio wrote: >> On 6/4/26 7:26 AM, Imran Shaik wrote: >>> Add support for Display clock controller and GPU clock controller nodes >>> on Qualcomm Shikra SoCs. >>> >>> Signed-off-by: Imran Shaik >>> --- [...] >>> +                      "gcc_disp_gpll0_clk_src", >>> +                      "gcc_disp_gpll0_div_clk_src", >>> +                      "dsi0_phy_pll_out_byteclk", >>> +                      "dsi0_phy_pll_out_dsiclk", >>> +                      "dsi1_phy_pll_out_byteclk", >>> +                      "dsi1_phy_pll_out_dsiclk", >>> +                      "sleep_clk"; >>> +            #clock-cells = <1>; >>> +            #reset-cells = <1>; >>> +            #power-domain-cells = <1>; >> >> DISP_CC also needs to source power from somewhere! >> > > The Shikra bindings aligns with the existing Agatti bindings, as it is a re-use. And the Shikra/Agatti DISPCC is on CX rail, and it will be always ON when APPS is active. Yes, it will be on, but currently the genpd performance state requests (i.e. RPMH states) go to /dev/null because DISP_CC is an orphan Konrad