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smtp.subspace.kernel.org; dkim=pass header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=PWvVjhEq; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DA30606A31A; Fri, 23 Oct 2026 11:25:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=PWvVjhEq Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7BCF81F01825; Fri, 23 Oct 2026 11:25:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1792754710; bh=W2nKm0rLN392hw5JmRVlu3U7b96TGQMs8eVI+K1UXmU=; h=Date:Subject:To:Cc:References:From:In-Reply-To; b=PWvVjhEqdNCWIJQohhYTxa8/jS+/m5syrySjHqxZiY25CQ1RbRA1T23IvLi5MoxQs wGdDgkjGIrJlqdGO+cCk6h7g8UWjh/9y6QiN7x+bpqwGAPpUKcHHpoGJTbaV6bKszm IbZ+0yPieE6eL3JRmgrUtlp9vvwR2AB8Bi8ibAUrINtuf2Ei+EGxmI/7Xt5JKQEKUL FP7HjVHha4l/OJsCUsXfMRqpPQ01cuThewl195hjXC0YafzA3GDZEwkVgZ5vaszMrW TidZCp47zvTK1FzTtsAOQW9f2vXYsDNFBWU5xxqBKH/KEM1skSt0ltPSWZ7vi9pgPd pSHDdWFXVaujg== Message-ID: <051bd988-9817-49e3-bfc4-0e3ca86bc91a@kernel.org> Date: Fri, 23 Oct 2026 13:25:00 +0200 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/8] i3c: renesas: Add RZ/G3L support To: Biju Das , wsa+renesas Cc: Diogo Ivo , Tommaso Merciai , Alexandre Belloni , Frank Li , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , "magnus.damm" , Stephen Boyd , Brian Masney , Jerome Brunet , Linus Walleij , "linux-i3c@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-renesas-soc@vger.kernel.org" , "linux-clk@vger.kernel.org" , "linux-gpio@vger.kernel.org" References: <20261020-divo-ssgrlpcsrc-2966-i3c-v1-0-30a47f25e515@renesas.com> <20261020-divo-ssgrlpcsrc-2966-i3c-v1-4-30a47f25e515@renesas.com> <20261023-thundering-axolotl-of-examination-aaa6ba@quoll> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 23/10/2026 13:01, Biju Das wrote: > Hi Wolfram, > >> -----Original Message----- >> From: Wolfram Sang >> Sent: 23 October 2026 11:46 >> Subject: Re: [PATCH 4/8] i3c: renesas: Add RZ/G3L support >> >> On Fri, Oct 23, 2026 at 10:28:16AM +0200, Krzysztof Kozlowski wrote: >>> On Tue, Oct 20, 2026 at 10:14:58AM +0100, Diogo Ivo wrote: >>>> Add support for the I3C Bus Interface on the Renesas RZ/G3L >>>> (R9A08G046) SoC by adding the renesas,r9a08g046-i3c compatible to >>>> the OF match table. >>>> >>>> The controller is very similar to the IP on the RZ/G3S. However, for >>>> instance the RZ/G3L variant has no HDR Exit Pattern detection interrupt: >>>> RZ/G3S exposes 17 interrupts, while RZ/G3L exposes 16. A RZ/G3L node >>>> therefore cannot be described with the RZ/G3S compatible, as its >>>> bindings require at least 17 interrupts. The same point applies to >>>> RZ/G3E, that requires 3 clocks while the RZ/G3L requires 2. >>>> >>>> From the driver point of view there is no difference between the two >>>> SoCs: the driver only consumes the tclk clock, the presetn and >>>> tresetn resets and seven named interrupts (resp, rx, tx, st, sp, >>>> tend, nack), all of which are among the 16 shared ones. No driver >>>> changes are needed besides the new compatible. >>>> >>>> Signed-off-by: Diogo Ivo >>>> --- >>>> drivers/i3c/master/renesas-i3c.c | 1 + >>>> 1 file changed, 1 insertion(+) >>>> >>>> diff --git a/drivers/i3c/master/renesas-i3c.c >>>> b/drivers/i3c/master/renesas-i3c.c >>>> index 4fddc1b4fdbb..80a6df1151bf 100644 >>>> --- a/drivers/i3c/master/renesas-i3c.c >>>> +++ b/drivers/i3c/master/renesas-i3c.c >>>> @@ -1625,6 +1625,7 @@ static const struct dev_pm_ops >>>> renesas_i3c_pm_ops = { >>>> >>>> static const struct of_device_id renesas_i3c_of_ids[] = { >>>> { .compatible = "renesas,r9a08g045-i3c" }, >>>> + { .compatible = "renesas,r9a08g046-i3c" }, >>> >>> So fully compatible? If so, drop this and express compatibility in the >>> bindings. >> >> Well, this SoC has 16 irqs / 2 clocks. The other variants have 16 / 3 and 17 / 2. So, to which one should >> it be compatible? I'd think 17 / 2 is the easier one. The number of inputs really does not matter here - all are anyway expressed in DTS. Question is whether these number makes a difference for driver. >> >> Or should we even refactor r9a08g047-i3c to be compatible with r9a08g045-i3c ? We currently don't use the >> third clock as well. That would mean deprecation of the old plain 'r9a08g047-i3c' binding, of course. >> >> Opinions? > > RZ/G3E I3C does not have analog filter compared to RZ/G3L and RZ/G3S > Moreover, it supports - High-speed mode (Hs-mode): 0 to 3.4 Mbps. Features define compatibility, but nevertheless this has to be addressed in the commit msg. That's why I referred to writing bindings in other patch. Best regards, Krzysztof