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[86.188.11.239]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4399c71ad07sm9794155f8f.16.2026.02.27.14.05.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Feb 2026 14:05:21 -0800 (PST) Message-ID: <051f77c615de15302ff7835757c130197df954a9.camel@linaro.org> Subject: Re: [PATCH v8 11/18] arm64: dts: qcom: x1e80100: Add CAMSS block definition From: Christopher Obbard To: Bryan O'Donoghue , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Konrad Dybcio , Vladimir Zapolskiy , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, Krzysztof Kozlowski Date: Fri, 27 Feb 2026 22:05:20 +0000 In-Reply-To: <20260225-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v8-11-95517393bcb2@linaro.org> References: <20260225-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v8-0-95517393bcb2@linaro.org> <20260225-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v8-11-95517393bcb2@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2-8 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Hi Bryan, On Wed, 2026-02-25 at 15:11 +0000, Bryan O'Donoghue wrote: > Add dtsi to describe the xe180100 CAMSS block >=20 > 4 x CSIPHY > 3 x TPG > 2 x CSID > 2 x CSID Lite > 2 x IFE > 2 x IFE Lite >=20 > Signed-off-by: Bryan O'Donoghue > --- Reviewed-by: Christopher Obbard Tested-by: Christopher Obbard > arch/arm64/boot/dts/qcom/hamoa.dtsi | 171 ++++++++++++++++++++++++++++++= ++++++ > 1 file changed, 171 insertions(+) >=20 > diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qc= om/hamoa.dtsi > index 9c5ebe1b48ecd..5fac814ce0f6b 100644 > --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi > +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi > @@ -16,6 +16,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -5562,6 +5563,176 @@ cci1_i2c1: i2c-bus@1 { > }; > }; > =20 > + camss: isp@acb6000 { > + compatible =3D "qcom,x1e80100-camss"; > + > + reg =3D <0 0x0acb6000 0 0x1000>, > + <0 0x0acb7000 0 0x2000>, > + <0 0x0acb9000 0 0x2000>, > + <0 0x0acbb000 0 0x2000>, > + <0 0x0acc6000 0 0x1000>, > + <0 0x0acca000 0 0x1000>, > + <0 0x0acf6000 0 0x1000>, > + <0 0x0acf7000 0 0x1000>, > + <0 0x0acf8000 0 0x1000>, > + <0 0x0ac62000 0 0x4000>, > + <0 0x0ac71000 0 0x4000>, > + <0 0x0acc7000 0 0x2000>, > + <0 0x0accb000 0 0x2000>; > + > + reg-names =3D "csid_wrapper", > + "csid0", > + "csid1", > + "csid2", > + "csid_lite0", > + "csid_lite1", > + "csitpg0", > + "csitpg1", > + "csitpg2", > + "vfe0", > + "vfe1", > + "vfe_lite0", > + "vfe_lite1"; > + > + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, > + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, > + <&camcc CAM_CC_CORE_AHB_CLK>, > + <&camcc CAM_CC_CPAS_AHB_CLK>, > + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, > + <&camcc CAM_CC_CPAS_IFE_0_CLK>, > + <&camcc CAM_CC_CPAS_IFE_1_CLK>, > + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, > + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, > + <&camcc CAM_CC_CSID_CLK>, > + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, > + <&gcc GCC_CAMERA_HF_AXI_CLK>, > + <&gcc GCC_CAMERA_SF_AXI_CLK>, > + <&camcc CAM_CC_IFE_0_CLK>, > + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, > + <&camcc CAM_CC_IFE_1_CLK>, > + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, > + <&camcc CAM_CC_IFE_LITE_CLK>, > + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, > + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, > + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; > + > + clock-names =3D "camnoc_nrt_axi", > + "camnoc_rt_axi", > + "core_ahb", > + "cpas_ahb", > + "cpas_fast_ahb", > + "cpas_vfe0", > + "cpas_vfe1", > + "cpas_vfe_lite", > + "cphy_rx_clk_src", > + "csid", > + "csid_csiphy_rx", > + "gcc_axi_hf", > + "gcc_axi_sf", > + "vfe0", > + "vfe0_fast_ahb", > + "vfe1", > + "vfe1_fast_ahb", > + "vfe_lite", > + "vfe_lite_ahb", > + "vfe_lite_cphy_rx", > + "vfe_lite_csid"; > + > + interrupts =3D , > + , > + , > + , > + , > + , > + , > + , > + ; > + > + interrupt-names =3D "csid0", > + "csid1", > + "csid2", > + "csid_lite0", > + "csid_lite1", > + "vfe0", > + "vfe1", > + "vfe_lite0", > + "vfe_lite1"; > + > + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONL= Y > + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, > + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names =3D "ahb", > + "hf_mnoc", > + "sf_mnoc", > + "sf_icp_mnoc"; > + > + iommus =3D <&apps_smmu 0x800 0x60>, > + <&apps_smmu 0x860 0x60>, > + <&apps_smmu 0x1860 0x60>, > + <&apps_smmu 0x18e0 0x00>, > + <&apps_smmu 0x19a0 0x20>; > + > + phys =3D <&csiphy0 PHY_TYPE_DPHY>, <&csiphy1 PHY_TYPE_DPHY>, > + <&csiphy2 PHY_TYPE_DPHY>, <&csiphy4 PHY_TYPE_DPHY>; > + phy-names =3D "csiphy0", "csiphy1", > + "csiphy2", "csiphy4"; > + > + power-domains =3D <&camcc CAM_CC_IFE_0_GDSC>, > + <&camcc CAM_CC_IFE_1_GDSC>, > + <&camcc CAM_CC_TITAN_TOP_GDSC>; > + power-domain-names =3D "ife0", > + "ife1", > + "top"; > + > + status =3D "disabled"; > + > + ports { > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + > + port@0 { > + reg =3D <0>; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + camss_csiphy0_inep0: endpoint@0 { > + reg =3D <0>; > + }; > + }; > + > + port@1 { > + reg =3D <1>; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + camss_csiphy1_inep0: endpoint@0 { > + reg =3D <0>; > + }; > + }; > + > + port@2 { > + reg =3D <2>; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + camss_csiphy2_inep0: endpoint@0 { > + reg =3D <0>; > + }; > + }; > + > + port@3 { > + reg =3D <3>; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + camss_csiphy4_inep0: endpoint@0 { > + reg =3D <0>; > + }; > + }; > + }; > + }; > + > csiphy0: csiphy@ace4000 { > compatible =3D "qcom,x1e80100-csi2-phy"; > reg =3D <0 0x0ace4000 0 0x2000>;