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X-CSE-ConnectionGUID: d1Uqyeg/SwOSKUPBD2gUgQ== X-CSE-MsgGUID: 6htGqkD6R+iohp52JwxGOQ== X-IronPort-AV: E=McAfee;i="6700,10204,11191"; a="24290494" X-IronPort-AV: E=Sophos;i="6.10,218,1719903600"; d="scan'208";a="24290494" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Sep 2024 18:26:08 -0700 X-CSE-ConnectionGUID: Zbwq4DIgSXW6ARspI58veg== X-CSE-MsgGUID: LuUwO+iXR0W5hj17TYD3SA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,218,1719903600"; d="scan'208";a="67057183" Received: from dapengmi-mobl1.ccr.corp.intel.com (HELO [10.124.229.37]) ([10.124.229.37]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Sep 2024 18:26:04 -0700 Message-ID: <0525e13d-7439-4b42-af69-85aa33f5d3c8@linux.intel.com> Date: Wed, 11 Sep 2024 09:26:02 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [Patch v3 0/4] Enable PMU for ArrowLake-H To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Kan Liang Cc: linux-kernel@vger.kernel.org, Andi Kleen , Yongwei Ma , Pawan Gupta , Dapeng Mi References: <20240820073853.1974746-1-dapeng1.mi@linux.intel.com> Content-Language: en-US From: "Mi, Dapeng" In-Reply-To: <20240820073853.1974746-1-dapeng1.mi@linux.intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 8/20/2024 3:38 PM, Dapeng Mi wrote: > No code changes comparing v2, just add back the missed reviewed-by. > > Changes: > v2 -> v3: > * Add Kan's review-by. > v1 -> v2: > * Change PMU name of 2nd atom uarch cores to "cpu_lowpower" (Peter) > * Rename "hybrid_small2" to "hybrid_tiny" (Peter) > * Rebase to 6.11-rc4 > > History: > * v2: https://lore.kernel.org/all/20240819145543.1833126-1-dapeng1.mi@linux.intel.com/ > * v1: https://lore.kernel.org/all/20240808140210.1666783-1-dapeng1.mi@linux.intel.com/ > > Dapeng Mi (4): > perf/x86: Refine hybrid_pmu_type defination > x86/cpu/intel: Define helper to get CPU core native ID > perf/x86/intel: Support hybrid PMU with multiple atom uarchs > perf/x86/intel: Add PMU support for ArrowLake-H > > arch/x86/events/intel/core.c | 129 ++++++++++++++++++++++++++++++++--- > arch/x86/events/intel/ds.c | 21 ++++++ > arch/x86/events/perf_event.h | 34 ++++++--- > arch/x86/include/asm/cpu.h | 6 ++ > arch/x86/kernel/cpu/intel.c | 15 ++++ > 5 files changed, 187 insertions(+), 18 deletions(-) > > > base-commit: 47ac09b91befbb6a235ab620c32af719f8208399 Hi Peter, could you please kindly review this new version patchset? Thanks.