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([2a01:e0a:982:cbb0:bf4e:5758:59ef:deb8]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a8e38428bsm4156433f8f.37.2025.01.10.02.12.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 10 Jan 2025 02:12:26 -0800 (PST) Message-ID: <0560bac7-ce4f-4b76-a6af-37ee4747dce9@linaro.org> Date: Fri, 10 Jan 2025 11:12:25 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Neil Armstrong Reply-To: neil.armstrong@linaro.org Subject: Re: [PATCH 2/2] drm/meson: vclk: fix precision in vclk calculations To: Maxime Ripard , Christian Hewitt Cc: Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Jernej Skrabec , dri-devel@lists.freedesktop.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20250110074458.3624094-1-christianshewitt@gmail.com> <20250110074458.3624094-3-christianshewitt@gmail.com> <20250110-flat-quantum-frigatebird-2432f1@houat> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <20250110-flat-quantum-frigatebird-2432f1@houat> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 10/01/2025 09:36, Maxime Ripard wrote: > Hi, > > On Fri, Jan 10, 2025 at 07:44:58AM +0000, Christian Hewitt wrote: >> Playing YUV420 @ 59.94 media causes HDMI output to lose sync >> with a fatal error reported: >> >> [ 89.610280] Fatal Error, invalid HDMI vclk freq 593406 >> >> In meson_encoder_hdmi_set_vclk the initial vclk_freq value is >> 593407 but YUV420 modes halve the value to 296703.5 and this >> is stored as int which loses precision by rounding down to >> 296703. The rounded value is later doubled to 593406 and then >> meson_encoder_hdmi_set_vclk sets an invalid vclk_freq value >> and the error triggers during meson_vlkc_setup validation. >> >> Fix precision in meson_encoder_hdmi_set_vclk by switching to >> unsigned long long KHz values instead of int MHz. As values >> for phy_freq are now more accurate we also need to handle an >> additional match scenario in meson_vclk_setup. >> >> Fixes: e5fab2ec9ca4 ("drm/meson: vclk: add support for YUV420 setup") >> Signed-off-by: Christian Hewitt >> --- >> drivers/gpu/drm/meson/meson_encoder_hdmi.c | 42 +++++++++++----------- >> drivers/gpu/drm/meson/meson_vclk.c | 3 +- >> 2 files changed, 23 insertions(+), 22 deletions(-) >> >> diff --git a/drivers/gpu/drm/meson/meson_encoder_hdmi.c b/drivers/gpu/drm/meson/meson_encoder_hdmi.c >> index 0593a1cde906..fa37cf975992 100644 >> --- a/drivers/gpu/drm/meson/meson_encoder_hdmi.c >> +++ b/drivers/gpu/drm/meson/meson_encoder_hdmi.c >> @@ -70,12 +70,12 @@ static void meson_encoder_hdmi_set_vclk(struct meson_encoder_hdmi *encoder_hdmi, >> { >> struct meson_drm *priv = encoder_hdmi->priv; >> int vic = drm_match_cea_mode(mode); >> - unsigned int phy_freq; >> - unsigned int vclk_freq; >> - unsigned int venc_freq; >> - unsigned int hdmi_freq; >> + unsigned long long vclk_freq; >> + unsigned long long phy_freq; >> + unsigned long long venc_freq; >> + unsigned long long hdmi_freq; >> >> - vclk_freq = mode->clock; >> + vclk_freq = mode->clock * 1000ULL; > > You should be using drm_hdmi_compute_mode_clock() here Yes in a second time, this simply fixes the actual calculations so it can be backported to stable kernel to make the feature work again. And yes at some point we should switch to hdmi helpers in a separate forward changeset. Neil > > > >> /* For 420, pixel clock is half unlike venc clock */ >> if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYYVYY8_0_5X24) >> @@ -85,8 +85,9 @@ static void meson_encoder_hdmi_set_vclk(struct meson_encoder_hdmi *encoder_hdmi, >> phy_freq = vclk_freq * 10; >> >> if (!vic) { >> - meson_vclk_setup(priv, MESON_VCLK_TARGET_DMT, phy_freq, >> - vclk_freq, vclk_freq, vclk_freq, false); >> + meson_vclk_setup(priv, MESON_VCLK_TARGET_DMT, phy_freq / 1000ULL, >> + vclk_freq / 1000ULL, vclk_freq / 1000ULL, >> + vclk_freq / 1000ULL, false); >> return; >> } >> >> @@ -107,12 +108,9 @@ static void meson_encoder_hdmi_set_vclk(struct meson_encoder_hdmi *encoder_hdmi, >> if (mode->flags & DRM_MODE_FLAG_DBLCLK) >> venc_freq /= 2; >> >> - dev_dbg(priv->dev, "vclk:%d phy=%d venc=%d hdmi=%d enci=%d\n", >> - phy_freq, vclk_freq, venc_freq, hdmi_freq, >> - priv->venc.hdmi_use_enci); >> - >> - meson_vclk_setup(priv, MESON_VCLK_TARGET_HDMI, phy_freq, vclk_freq, >> - venc_freq, hdmi_freq, priv->venc.hdmi_use_enci); >> + meson_vclk_setup(priv, MESON_VCLK_TARGET_HDMI, phy_freq / 1000ULL, >> + vclk_freq / 1000ULL, venc_freq / 1000ULL, hdmi_freq / 1000ULL, >> + priv->venc.hdmi_use_enci); >> } >> >> static enum drm_mode_status meson_encoder_hdmi_mode_valid(struct drm_bridge *bridge, >> @@ -122,10 +120,10 @@ static enum drm_mode_status meson_encoder_hdmi_mode_valid(struct drm_bridge *bri >> struct meson_encoder_hdmi *encoder_hdmi = bridge_to_meson_encoder_hdmi(bridge); >> struct meson_drm *priv = encoder_hdmi->priv; >> bool is_hdmi2_sink = display_info->hdmi.scdc.supported; >> - unsigned int phy_freq; >> - unsigned int vclk_freq; >> - unsigned int venc_freq; >> - unsigned int hdmi_freq; >> + unsigned long long vclk_freq; >> + unsigned long long phy_freq; >> + unsigned long long venc_freq; >> + unsigned long long hdmi_freq; >> int vic = drm_match_cea_mode(mode); >> enum drm_mode_status status; >> >> @@ -149,7 +147,7 @@ static enum drm_mode_status meson_encoder_hdmi_mode_valid(struct drm_bridge *bri >> } else if (!meson_venc_hdmi_supported_vic(vic)) >> return MODE_BAD; >> >> - vclk_freq = mode->clock; >> + vclk_freq = mode->clock * 1000ULL; > > And here too. > > Maxime