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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: MJ9vj_M7Egse7LXmwulFs1UZLZYcynkC X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE2MDAzNCBTYWx0ZWRfX5c3D2G+syfgz T+4ODvGjCEnZZSF44FBrPushldFTa37u0st2LIaqGXq3S3jYObDbNyvK0Tb+hLj/u/vCf6jkCft VSGQXoZ0FpXdTpwjSDlGwLdrk5/3ACkKpXCbZJAp9m+EtJV9L84ufyJk6IJBYiSW+2qr2i9ZTI1 IMDix+g8aKDOeZp2eo7332AfUfSudP7k1ijNmF369vN+DhcHrKcUJS/AAuqpG8eZgjyNC/I0taV xC4+0dvZRp1kG5fq/PQu+dNj58iVkE798dOQJTTjToOgQO41TWOSVnKUKi242BJM19f2BoOLjQl FcMGy5wSYZA4bU1e5sT8Ym3YAUtN802nysbYa+loaxGTWqdu+2lYZMVGMm2ltTNBT1LBP0zV+d/ 9NwNP3w/xSrrNwm8I2fPzMTOu19gKdsZ4+L7tqIFHDwTDBCf4odq7Zc+8TNRSMbJCPgh02qe6P2 GB1wDG1UQHs/j44Fc8g== X-Proofpoint-GUID: MJ9vj_M7Egse7LXmwulFs1UZLZYcynkC X-Authority-Analysis: v=2.4 cv=R5qWitRX c=1 sm=1 tr=0 ts=6ad1e44b cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=Tt5JBQAfAAAA:8 a=EUspDBNiAAAA:8 a=rBtVOrUcsPcThs3KVNEA:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 a=kpHMOrJS8sLNr5ru0mYA:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE2MDAzNCBTYWx0ZWRfX50MAlCdp8DB5 kCBgLUs3hdh88GKDJhpS4sny+M1rr7bynHiJxKWdFHsNMtF4nX0S0kziyuMzExK70z+NjQCNG97 VCbsFzasbSz4soo3EJTnsh52cJ8z4O0= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-14_01,2026-10-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 suspectscore=0 phishscore=0 adultscore=0 malwarescore=0 clxscore=1015 bulkscore=0 priorityscore=1501 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610160034 On 10/16/26 8:01 AM, Demeter Barna via B4 Relay wrote: > From: Demeter Barna > > Without them nothing votes for the CPUs' memory paths and DDR stays at > what other clients request. Vote for CPU-to-LLCC, LLCC-to-DDR and L3 > with the CPU frequency, as on SM8550 and SM8650. > > The frequencies are the cpufreq-hw LUT; the LLCC, DDR (LPDDR5) and L3 > levels follow the downstream memory latency tables. > > Assisted-by: LLM > Signed-off-by: Demeter Barna > --- Reviewed-by: Konrad Dybcio Konrad