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Mon, 29 Dec 2025 08:47:23 -0800 (PST) Received: from [192.168.88.32] ([169.155.232.231]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4324ea227casm62923317f8f.15.2025.12.29.08.47.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 29 Dec 2025 08:47:22 -0800 (PST) Message-ID: <0572ccee-d6ab-4921-b44e-c8641622940f@redhat.com> Date: Mon, 29 Dec 2025 17:47:21 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH net v2 2/3] octeon_ep: ensure dbell BADDR updation To: Vimlesh Kumar , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: sedara@marvell.com, srasheed@marvell.com, hgani@marvell.com, Veerasenareddy Burru , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski References: <20251219100751.3063135-1-vimleshk@marvell.com> <20251219100751.3063135-3-vimleshk@marvell.com> Content-Language: en-US From: Paolo Abeni In-Reply-To: <20251219100751.3063135-3-vimleshk@marvell.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 12/19/25 11:07 AM, Vimlesh Kumar wrote: > @@ -327,11 +328,13 @@ static void octep_setup_iq_regs_cnxk_pf(struct octep_device *oct, int iq_no) > } > > /* Setup registers for a hardware Rx Queue */ > -static void octep_setup_oq_regs_cnxk_pf(struct octep_device *oct, int oq_no) > +static int octep_setup_oq_regs_cnxk_pf(struct octep_device *oct, int oq_no) > { > u64 reg_val; > u64 oq_ctl = 0ULL; > + u64 reg_ba_val; > u32 time_threshold = 0; > + unsigned long t_out_jiffies; > struct octep_oq *oq = oct->oq[oq_no]; Ouch, the above variable declaration follows the exact opposite of the mandated style, please use the reverse christmas tree order. Similar nit on the next patch. > > oq_no += CFG_GET_PORTS_PF_SRN(oct->conf); > @@ -343,6 +346,33 @@ static void octep_setup_oq_regs_cnxk_pf(struct octep_device *oct, int oq_no) > reg_val = octep_read_csr64(oct, CNXK_SDP_R_OUT_CONTROL(oq_no)); > } while (!(reg_val & CNXK_R_OUT_CTL_IDLE)); > } > + octep_write_csr64(oct, CNXK_SDP_R_OUT_WMARK(oq_no), oq->max_count); > + /* Wait for WMARK to get applied */ > + usleep_range(10, 15); > + > + octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_BADDR(oq_no), > + oq->desc_ring_dma); > + octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_RSIZE(oq_no), > + oq->max_count); > + reg_ba_val = octep_read_csr64(oct, CNXK_SDP_R_OUT_SLIST_BADDR(oq_no)); > + > + if (reg_ba_val != oq->desc_ring_dma) { > + t_out_jiffies = jiffies + 10 * HZ; > + do { > + if (reg_ba_val == ULLONG_MAX) > + return -EFAULT; > + octep_write_csr64(oct, > + CNXK_SDP_R_OUT_SLIST_BADDR(oq_no), > + oq->desc_ring_dma); > + octep_write_csr64(oct, > + CNXK_SDP_R_OUT_SLIST_RSIZE(oq_no), > + oq->max_count); > + reg_ba_val = > + octep_read_csr64(oct, > + CNXK_SDP_R_OUT_SLIST_BADDR(oq_no)); > + } while ((reg_ba_val != oq->desc_ring_dma) && > + time_before(jiffies, t_out_jiffies)); If a timeout happens - !time_before(jiffies, t_out_jiffies) - execution proceed even if reg_ba_val != oq->desc_ring_dma; I guess you should error out istead?!? Otherwise you should at least add a comment for future memory explaining why that is correct. Similar question on the next patch. /P