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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=Jr3Bas4C c=1 sm=1 tr=0 ts=6a66e041 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=BpNlaLRTw972n_5ZLSgA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI3MDA0MSBTYWx0ZWRfX9LurZqhZ/Hm/ mSpHnwSkLop7qO7YtgdMyoVN2DFAMwepld7dUXyines6odtpT/AfAcP1az3YWoPH8HUTXg0TFnV 1fQIk/g9v02p/kfEtEPxudBQZ10vj2A= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI3MDA0MSBTYWx0ZWRfXzt3589byhiS0 jLYrDy/dSa6Rg5fq4T8Xuctyhah3eIlXWNq8SuomicGZO6Q3xag2Nk5XDfct5wL6vb+bHoheBJr UIwo9w/i0ZK3zgn+SvWlhWS7fMRayBcb3+ok9KfOrKcWpu7y8Wp50KEfgUqXLBffHq89ldpS73i YyXYooehM1LxX/kC9Ni/80z8KeSZfSQeMufB/8zXFPoMpSQBziNwJ7dqx9aIlggn6n4KqW8FQ7N /j1kXFPH46DbiRID2XWNMQt22Izj682irb27q/+mpo+tB5nw6EmYrxIP48nqiKO5L+FVuAYKGv1 dG8ix+i6dwDgcHFs3+9aUd+HXpiHZy8ypvIeQuFXUAbL3oiHh6bFXuJZtnAtEdXrL3Ewfop5R7e X7FMeOlAbR00ziuixyH20gyjlDQLGpgJuyjGTSam1WihdcWiRvY95qtenejkfQelhrEB7fYxiRb Bn51yZqz7Su20j4WXgA== X-Proofpoint-ORIG-GUID: giCXx4VWfOBbWW1P7LwzRtEeRumGY1Cc X-Proofpoint-GUID: giCXx4VWfOBbWW1P7LwzRtEeRumGY1Cc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-27_01,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 malwarescore=0 spamscore=0 adultscore=0 impostorscore=0 phishscore=0 clxscore=1015 bulkscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607270041 On 6/29/2026 12:02 PM, Krzysztof Kozlowski wrote: > On 28/06/2026 16:39, Viken Dadhaniya wrote: >> +description: >> + The Qualcomm I2C slave controller is a dedicated hardware IP found on >> + Qualcomm SoCs that operates exclusively as an I2C slave device on the bus. >> + It supports FIFO (PIO) mode for data transfer and does not function as an >> + I2C master. >> + >> +properties: >> + compatible: >> + const: qcom,i2c-slave > > Such compatible makes little sense in upstream. Please look at other > bindings how to properly create a compatible. This has to be device > specific. > Sure, will update with an SoC-specific compatible string (e.g., qcom,qdu1000-i2c-target) in the next revision. >> + >> + reg: >> + maxItems: 1 >> + >> + interrupts: >> + maxItems: 1 >> + >> + clocks: >> + items: >> + - description: XO clock for I2C slave >> + - description: AHB clock for I2C slave >> + >> + clock-names: >> + items: >> + - const: sm_bus_xo_clk >> + - const: sm_bus_ahb_clk > > Look at other bindings. > Sure, updated the clock names to xo and ahb in the next revision. >> + >> + qcom,slave-addr: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + description: >> + The 7-bit I2C slave address programmed into the controller's device >> + address register. This controller operates exclusively as an I2C slave >> + and has no child nodes, so the standard 'reg' property cannot be used >> + to convey the I2C address (it is already used for the MMIO register >> + range). The address is configurable at runtime via a hardware register. >> + minimum: 0x08 >> + maximum: 0x77 >> + >> + interconnects: >> + maxItems: 1 >> + >> + interconnect-names: >> + const: i2c-slave-config > > i2c > Sure, will update to i2c in the next revision. >> + >> + pinctrl-0: true >> + pinctrl-1: true >> + >> + pinctrl-names: >> + minItems: 1 >> + items: >> + - const: default >> + - const: sleep >> + >> +required: >> + - compatible >> + - reg >> + - interrupts >> + - clocks >> + - clock-names >> + - qcom,slave-addr >> + - interconnects >> + - interconnect-names >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include >> + #include >> + #include >> + >> + i2c-slave@88ca000 { > > You need to fix your terminology everywhere... > Will update in the next revision. > > Best regards, > Krzysztof