From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755561AbdESNmM (ORCPT ); Fri, 19 May 2017 09:42:12 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:31656 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755432AbdESNmI (ORCPT ); Fri, 19 May 2017 09:42:08 -0400 From: Patrice CHOTARD To: Ard Biesheuvel CC: "linux@armlinux.org.uk" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Christophe PRIOUZEAU , Christophe KERELLO , Vikas MANOCHA , "Patrick DELAUNAY" Subject: Re: [PATCH 1/1] ARM: compressed/head.S: fix __nop macro rept number for ARMv7M Thread-Topic: [PATCH 1/1] ARM: compressed/head.S: fix __nop macro rept number for ARMv7M Thread-Index: AQHSvaKPWLuUaD+E+UyEsXtLzXqRKKHwRBoAgAmviwCAAbrKAA== Date: Fri, 19 May 2017 13:41:29 +0000 Message-ID: <058263e4-458a-7939-1c1c-7bcd100cf2c5@st.com> References: <1493110893-21857-1-git-send-email-patrice.chotard@st.com> In-Reply-To: Accept-Language: fr-FR, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: user-agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.1.1 x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.75.127.49] Content-Type: text/plain; charset="utf-8" Content-ID: <1C22B55D609D1E4D868CFB8AF7DCE4B2@st.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-05-19_08:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id v4JDgHw6008598 Hi Ard On 05/18/2017 01:16 PM, Ard Biesheuvel wrote: > On 12 May 2017 at 08:22, Patrice CHOTARD wrote: >> Hi all >> >> It's a gentle reminder to not forgot this patch. >> >> Thanks >> >> Patrice >> >> On 04/25/2017 11:01 AM, patrice.chotard@st.com wrote: >>> From: Patrice Chotard >>> >>> In zImage, _magic_sig is located at offset 0x24. >>> But for ARMv7M architecture which enable CPU_THUMBONLY >>> and !EFI_STUB kernel flag, _magic_sig is located at offset 0x14 >>> >>> 00000000 00 46 00 46 00 46 00 46 00 46 00 46 00 46 0f f2 |.F.F.F.F.F.F.F.ò| >>> 00000010 15 0c 60 47 18 28 6f 01 00 00 00 00 28 5c 0e 00 |..`G.(o.....(\..| >>> 00000020 01 02 03 04 0f 46 90 46 00 00 00 00 00 00 00 00 |.....F.F........| >>> >>> Reproduced with stm32_defconfig with XIP_KERNEL flag disabled. >>> >>> To restore correct _magic_sig offset at 0x24, we add 8 additional >>> "mov r0, r0" instruction. >>> >>> Signed-off-by: Patrice Chotard >>> --- >>> arch/arm/boot/compressed/head.S | 3 ++- >>> 1 file changed, 2 insertions(+), 1 deletion(-) >>> >>> diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S >>> index 9150f97..5d9cda3 100644 >>> --- a/arch/arm/boot/compressed/head.S >>> +++ b/arch/arm/boot/compressed/head.S >>> @@ -127,7 +127,8 @@ >>> AR_CLASS( .arm ) >>> start: >>> .type start,#function >>> - .rept 7 >>> + ARM( .rept 7) >>> + THUMB( .rept 15) >>> > > Could you try using W(mov) instead of mov in the definition of __nop ? If i use W(mov) instead of mov in __nop macro, i need to add one additional "mov r0,r0" in THUMB case as following : start: .type start,#function .rept 7 __nop .endr ARM( mov r0, r0 ) ARM( b 1f ) + THUMB( mov r0, r0 ) THUMB( badr r12, 1f ) THUMB( bx r12 ) .word _magic_sig @ Magic numbers to help the loader .word _magic_start @ absolute load/run zImage address .word _magic_end @ zImage end address .word 0x04030201 @ endianness flag Which implementation do you prefer ? Thanks Patrice