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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BL02EPF00021F68.mail.protection.outlook.com (10.167.249.4) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.92.5 via Frontend Transport; Fri, 5 Jun 2026 03:41:41 +0000 Received: from satlexmb10.amd.com (10.181.42.219) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Thu, 4 Jun 2026 22:41:41 -0500 Received: from satlexmb08.amd.com (10.181.42.217) by satlexmb10.amd.com (10.181.42.219) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Thu, 4 Jun 2026 22:41:40 -0500 Received: from [10.136.33.4] (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.41 via Frontend Transport; Thu, 4 Jun 2026 22:41:38 -0500 Message-ID: <05977a61-5bc2-4a56-9105-f9731d1b12dd@amd.com> Date: Fri, 5 Jun 2026 09:11:37 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/2] cpufreq/amd-pstate: Fix EPP initialization for shared memory systems To: Mario Limonciello , Marco Scardovi CC: , , , , , , , References: <4cb9459c-f471-478a-9670-58d898619f45@amd.com> <2e3a5f9a-69fe-4790-8b8b-2d1622977a2f@amd.com> Content-Language: en-US From: K Prateek Nayak In-Reply-To: Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ReAMjyf6qHaKW3SYpoqORoPbkLO/gcicnkF4ItTrXYfCpaMghoGysvgwQ91hSHg5yOQGM6ZMEv5IaXZvN1Do9NpFrboCVRGeYEeeoN+Pu/8jP6uCSTIWjIVfQ/b+SEInbmN1v0I++L6N9H5mWSPYCLGc8YLaQGXXIje/En9f/jq2tZlELxzKNcy+0ZblGFAuCNl5DGKqOreIIwSmNWLZPvR+v4DHo+yC3nCXpeHYa2RuQ7ftbjE4NyqAchnygFaYo3OTD9W04favigqFd4/oCEQlSg6VCUEmdwR+31BGc6t+6BDptqXmmYTWeGHrpzfz5p0yEZTJZH1gF76szqjspHjN41sYqCzvhXfdzYlGc3WqrEhOyB1ibfOFLh/E/2HABl5KuuYMZK/oU8EMaMQlA4dHXlyBrt24kc1pOWhu4QzddIhzN4eAjhdvvjcCREFO X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jun 2026 03:41:41.7740 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 27894d5d-6db5-4083-749c-08dec2b45b7f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F68.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5739 Hello Mario, On 6/5/2026 12:13 AM, Mario Limonciello wrote: > So at least for patch 1 if you run dynamic epp, and are plugged into a wall > you start out on EPP 0, but I'm pretty sure that's usually the firmware > default anyway.  But this gives me a (better?) idea.  How about we just > read the EPP from the firmware initially at startup? I'm looking at the ACPI tables across various generations and, from Zen4 onward, we stopped including the optional AUTO_SEL_ENABLE register as the platforms introduced MSR based interfaces. The Energy Performance Preference Register definition reads: If supported, contains a resource descriptor with a single Register() descriptor that describes a register to which OSPM writes a value to control the Energy vs. Performance preference of the platform’s energy efficiency and performance optimization policies when *Autonomous Selection is enabled*. I think, the shmem platforms should call cppc_set_auto_sel(cpu, 1) just as a safety during epp_cpu_init just to ensure we are not missing out on enabling it if there is some dependency there. > > Something like this: > > ╰─❯ git diff > diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c > index 3f06e33f47120..0e32f7f92651b 100644 > --- a/drivers/cpufreq/amd-pstate.c > +++ b/drivers/cpufreq/amd-pstate.c > @@ -1939,6 +1939,8 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) > >         policy->boost_supported = READ_ONCE(cpudata->boost_supported); > > +       WRITE_ONCE(cpudata->cppc_req_cached, FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, amd_pstate_get_epp(cpudata))); > + >         /* >          * Set the policy to provide a valid fallback value in case >          * the default cpufreq governor is neither powersave nor performance. > Building on top of your suggestion: diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 72df461e7b39..27ed0db02bcb 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1882,6 +1882,7 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) struct amd_cpudata *cpudata; union perf_cached perf; struct device *dev; + s16 default_epp; int ret; /* @@ -1928,9 +1929,22 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) /* It will be updated by governor */ policy->cur = policy->cpuinfo.min_freq; - policy->boost_supported = READ_ONCE(cpudata->boost_supported); + /* Cache the firmware programmed EPP */ + default_epp = amd_pstate_get_epp(cpudata); + FIELD_MODIFY(AMD_CPPC_EPP_PERF_MASK, &cpudata->cppc_req_cached, default_epp); + + /* + * Shared memory based systems may require the AUTO_SEL_ENABLE register + * to be toggled on to function correctly. Since the first call to + * amd_pstate_set_epp() may bail out early if the desired EPP is + * same as the one configured by the firmware, attempt to toggle the + * AUTO_SEL_ENABLE here, independent of EPP programming. + */ + if (!cpu_feature_enabled(X86_FEATURE_CPPC)) + cppc_set_auto_sel(policy->cpu, 1); + /* * Set the policy to provide a valid fallback value in case * the default cpufreq governor is neither powersave nor performance. @@ -1938,7 +1952,7 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) if (amd_pstate_acpi_pm_profile_server() || amd_pstate_acpi_pm_profile_undefined()) { policy->policy = CPUFREQ_POLICY_PERFORMANCE; - cpudata->epp_default_ac = cpudata->epp_default_dc = amd_pstate_get_epp(cpudata); + cpudata->epp_default_ac = cpudata->epp_default_dc = default_epp; cpudata->current_profile = PLATFORM_PROFILE_PERFORMANCE; } else { policy->policy = CPUFREQ_POLICY_POWERSAVE; --- I'm not sure whether guided mode needs this but I'll get my hands on a Zen2 part to test this out. -- Thanks and Regards, Prateek