Re: [PATCH v3] PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0)

[Siddharth Vadapalli <s-vadapalli@ti.com>]

On Thu, Jun 27, 2024 at 03:35:28PM +0200, Jan Kiszka wrote:
> From: Kishon Vijay Abraham I <kishon@ti.com>
> 
> Errata #i2037 in AM65x/DRA80xM Processors Silicon Revision 1.0
> (SPRZ452D_July 2018_Revised December 2019 [1]) mentions when an
> inbound PCIe TLP spans more than two internal AXI 128-byte bursts,
> the bus may corrupt the packet payload and the corrupt data may
> cause associated applications or the processor to hang.
> 
> The workaround for Errata #i2037 is to limit the maximum read
> request size and maximum payload size to 128 Bytes. Add workaround

s/128 Bytes/128 bytes
as indicated by Krzysztof on the v1 patch at:
https://lore.kernel.org/linux-pci/YF2K6+R1P3SNUoo5@rocinante/

> for Errata #i2037 here. The errata and workaround is applicable
> only to AM65x SR 1.0 and later versions of the silicon will have
> this fixed.

[...]

> 
> +	/*
> +	 * Memory transactions fail with PCI controller in AM654 PG1.0
> +	 * when MRRS is set to more than 128 Bytes. Force the MRRS to
> +	 * 128 Bytes in all downstream devices.

s/128 Bytes/128 bytes
as indicated by Krzysztof on the v1 patch at:
https://lore.kernel.org/linux-pci/YF2K6+R1P3SNUoo5@rocinante/

> +	 */
> +	if (pci_match_id(am6_pci_devids, bridge)) {
> +		bridge_dev = pci_get_host_bridge_device(dev);
> +		if (!bridge_dev && !bridge_dev->parent)
> +			return;
> +
> +		ks_pcie = dev_get_drvdata(bridge_dev->parent);
> +		if (!ks_pcie)
> +			return;
> +
> +		val = ks_pcie_app_readl(ks_pcie, PID);
> +		val &= RTL;
> +		val >>= RTL_SHIFT;
> +		if (val != AM6_PCI_PG1_RTL_VER)
> +			return;
> +
> +		if (pcie_get_readrq(dev) > 128) {
> +			dev_info(&dev->dev, "limiting MRRS to 128 bytes\n");

Thank you for adding "bytes" in the above line.

> +			pcie_set_readrq(dev, 128);
> +		}
> +	}
>  }
>  DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk);

Regards,
Siddharth.