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([2600:8803:e7e4:500:e782:93d8:7c2f:f9df]) by smtp.gmail.com with ESMTPSA id 5614622812f47-450fff8d592sm2073533b6e.12.2025.11.21.14.32.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 21 Nov 2025 14:32:32 -0800 (PST) Message-ID: <05fae891-a4e6-439d-97da-6259370f68b5@baylibre.com> Date: Fri, 21 Nov 2025 16:32:30 -0600 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/2] iio: Add support for TI ADS1X18 ADCs To: Kurt Borja , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tobias Sperling Cc: =?UTF-8?Q?Nuno_S=C3=A1?= , Andy Shevchenko , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Cameron References: <20251121-ads1x18-v1-0-86db080fc9a4@gmail.com> Content-Language: en-US From: David Lechner In-Reply-To: <20251121-ads1x18-v1-0-86db080fc9a4@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 11/21/25 11:16 AM, Kurt Borja wrote: > Hi, > > This series adds a new driver for TI ADS1X18 SPI devices. > > This is my first time contributing to the IIO subsystem and making > dt-bindings documentation, so (don't) go easy on me :p. I actually had these parts on my radar, so happy to help you out. Unfortunately, I don't have the hardware for testing though. The first thing I was going to do was check the existing drivers to make sure that there isn't one already that has a compatible register layout. I have a feeling we won't find one, but would be good to mention that in the cover to justify adding a new driver. There are a couple of similar TI ADCs on the mailing list right now, but they are IMHO just slightly too different to share a driver, but would be good to look at just to make things are consistent on a high level. > > As explained in Patch 2 changelog, the DRDY interrupt line is shared > with the MOSI pin. This awkward quirk is also found on some Analog > Devices sigma-delta SPI ADCs, so the interrupt and trigger design is > inspired by those. Yup, that seems to be the best way we know how to handle this.