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Tue, 15 Oct 2019 02:58:21 +0000 (GMT) From: "Pankaj Dubey" To: "'Lorenzo Pieralisi'" Cc: , , , , , , , "'Anvesh Salveru'" In-Reply-To: <20191014151349.GA2928@e121166-lin.cambridge.arm.com> Subject: RE: [PATCH v2] PCI: dwc: Add support to add GEN3 related equalization quirks Date: Tue, 15 Oct 2019 08:28:20 +0530 Message-ID: <062d01d58304$683306a0$389913e0$@samsung.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQGpt1aXoM8skySOYXB2n3mBAGb+JQKeZApdAfxzZgCnjcJR0A== Content-Language: en-us X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrLKsWRmVeSWpSXmKPExsWy7bCmhu5506WxBrMPqVs0/9/OanF210JW iyVNGRa77nawW6z4MpPd4vKuOWwWZ+cdZ7N48/sFu8W17bwOnB5r5q1h9Ng56y67x4JNpR69 ze/YPPq2rGL02LL/M6PH501yAexRXDYpqTmZZalF+nYJXBltW04zF7QrV1z/84KpgfGNTBcj J4eEgInE4fnrmEFsIYHdjBLTv6R3MXIB2Z8YJTa+fcgG4XxjlDg9+wUjTMf+/xeYIRJ7GSUu zfgB5bxmlNh54jILSBWbgL7EuR/zWEFsEQFTiSOvPrKDFDELvGOU2Pv2IFgRp4CTxOalW8GW CwuES5zYtgfMZhFQlZgy4w7QOg4OXgFLiXvHwMK8AoISJ2c+AWtlFpCX2P52DjPERQoSP58u g9rlJHF1wz92iBpxiZdHj4DtlRBoZ5dY1/4DbKaEgIvExXZ5iF5hiVfHt7BD2FISL/vboOx8 iR+LJzFD9LYwSkw+PpcVImEvceDKHBaQOcwCmhLrd+lD7OKT6P39hAliPK9ER5sQRLWaxPfn Z6DOlJF42LyUCcL2kHjwvZFlAqPiLCSfzULy2SwkH8xCWLaAkWUVo2RqQXFuemqxaYFxXmq5 XnFibnFpXrpecn7uJkZwotLy3sG46ZzPIUYBDkYlHl6BliWxQqyJZcWVuYcYJTiYlUR454OE eFMSK6tSi/Lji0pzUosPMUpzsCiJ805ivRojJJCeWJKanZpakFoEk2Xi4JRqYOT6ddIuf53F 6TuTzOZYv2iNb/6WMaV16hVjvplT755ZyDcprnLB9cefpCIvnLxjvjzmk7+XfW64u/+dZrOV MuUmVXt9LvVqHDgbWLhHWvvG3JUiD85VlXW85Xt7ZOW1y8J6ai6fGGXY806/eHmC9ykvA/vy LvEknVXXzZdMcc2OejfV9O8v9z4lluKMREMt5qLiRAANC8LmUAMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrAIsWRmVeSWpSXmKPExsWy7bCSnO4506WxBncvmVo0/9/OanF210JW iyVNGRa77nawW6z4MpPd4vKuOWwWZ+cdZ7N48/sFu8W17bwOnB5r5q1h9Ng56y67x4JNpR69 ze/YPPq2rGL02LL/M6PH501yAexRXDYpqTmZZalF+nYJXBltW04zF7QrV1z/84KpgfGNTBcj J4eEgInE/v8XmLsYuTiEBHYzSmzZ8psNIiEjMXn1ClYIW1hi5b/n7BBFLxklLq/YzgSSYBPQ lzj3Yx5YkYiAqcSRVx/BipgFvjFKrHg8nQ2i4wKjxIcDexhBqjgFnCQ2L93KDGILC4RK/P/1 BsxmEVCVmDLjDlANBwevgKXEvWNgYV4BQYmTM5+wgISZBfQk2jaCTWEWkJfY/nYOM8RxChI/ ny6DusFJ4uqGf+wQNeISL48eYZ/AKDwLyaRZCJNmIZk0C0nHAkaWVYySqQXFuem5xYYFhnmp 5XrFibnFpXnpesn5uZsYwfGmpbmD8fKS+EOMAhyMSjy8Ai1LYoVYE8uKK3MPMUpwMCuJ8M4H CfGmJFZWpRblxxeV5qQWH2KU5mBREud9mncsUkggPbEkNTs1tSC1CCbLxMEp1cBo47Nw1t7k /zpBfa+1pe+cfGEmNffI4mm52VuK7rotu+n2NXAuu95cWYPX/3iO/VfW5jr03HAeT8K3rKz5 XYv2cV5b9n2fV9J6zQc30wrNlohmzNdb1p9S4fLKrHvTg+XlOtvuF5fyztP25Z16vKrqsFq6 6fq/vnXBO46vLHyZLn2qrMh2/14eJZbijERDLeai4kQAn2shurMCAAA= X-CMS-MailID: 20191015025822epcas5p3e076ffcca43610c3869db30ddda3263e X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P X-CMS-RootMailID: 20191014071838epcas5p2901e45c978e5a9d6dfbdde2dadea6d9d References: <1571037509-20284-1-git-send-email-pankaj.dubey@samsung.com> <20191014151349.GA2928@e121166-lin.cambridge.arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Lorenzo Pieralisi > Sent: Monday, October 14, 2019 8:44 PM > To: Pankaj Dubey > Cc: linux-pci@vger.kernel.org; linux-kernel@vger.kernel.org; > bhelgaas@google.com; andrew.murray@arm.com; > gustavo.pimentel@synopsys.com; jingoohan1@gmail.com; vidyas@nvidia.com; > Anvesh Salveru > Subject: Re: [PATCH v2] PCI: dwc: Add support to add GEN3 related equalization > quirks > > On Mon, Oct 14, 2019 at 12:48:29PM +0530, Pankaj Dubey wrote: > > From: Anvesh Salveru > > > > In some platforms, PCIe PHY may have issues which will prevent linkup > > to happen in GEN3 or higher speed. In case equalization fails, link > > will fallback to GEN1. > > > > DesignWare controller gives flexibility to disable GEN3 equalization > > completely or only phase 2 and 3 of equalization. > > > > This patch enables the DesignWare driver to disable the PCIe GEN3 > > equalization by enabling one of the following quirks: > > - DWC_EQUALIZATION_DISABLE: To disable GEN3 equalization all phases > > - DWC_EQ_PHASE_2_3_DISABLE: To disable GEN3 equalization phase 2 & 3 > > > > Platform drivers can set these quirks via "quirk" variable of "dw_pcie" > > struct. > > > > Signed-off-by: Anvesh Salveru > > Signed-off-by: Pankaj Dubey > > Acked-by: Gustavo Pimentel > > Reviewed-by: Andrew Murray > > Reviewed-by: Vidya Sagar > > --- > > Changes w.r.t v1: > > - Rebased on latest linus/master > > - Added Reviewed-by and Acked-by > > > > drivers/pci/controller/dwc/pcie-designware.c | 12 ++++++++++++ > > drivers/pci/controller/dwc/pcie-designware.h | 9 +++++++++ > > 2 files changed, 21 insertions(+) > > So this is v3 not v2, right ? > Yes, you are right. I missed this. This can be discarded, I will resend the patch with v3 tag. > Here is v2: > > https://protect2.fireeye.com/url?k=47b7cdf58f33e5e1.47b646ba- > 8ad463719e64eba8&u=https://patchwork.ozlabs.org/patch/1161958/ > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c > > b/drivers/pci/controller/dwc/pcie-designware.c > > index 820488d..e247d6d 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware.c > > +++ b/drivers/pci/controller/dwc/pcie-designware.c > > @@ -556,4 +556,16 @@ void dw_pcie_setup(struct dw_pcie *pci) > > PCIE_PL_CHK_REG_CHK_REG_START; > > dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, > val); > > } > > + > > + if (pci->quirk & DWC_EQUALIZATION_DISABLE) { > > + val = dw_pcie_readl_dbi(pci, PCIE_PORT_GEN3_RELATED); > > + val |= PORT_LOGIC_GEN3_EQ_DISABLE; > > + dw_pcie_writel_dbi(pci, PCIE_PORT_GEN3_RELATED, val); > > + } > > + > > + if (pci->quirk & DWC_EQ_PHASE_2_3_DISABLE) { > > + val = dw_pcie_readl_dbi(pci, PCIE_PORT_GEN3_RELATED); > > + val |= PORT_LOGIC_GEN3_EQ_PHASE_2_3_DISABLE; > > + dw_pcie_writel_dbi(pci, PCIE_PORT_GEN3_RELATED, val); > > + } > > } > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h > > b/drivers/pci/controller/dwc/pcie-designware.h > > index 5a18e94..7d3fe6f 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware.h > > +++ b/drivers/pci/controller/dwc/pcie-designware.h > > @@ -29,6 +29,10 @@ > > #define LINK_WAIT_MAX_IATU_RETRIES 5 > > #define LINK_WAIT_IATU 9 > > > > +/* Parameters for GEN3 related quirks */ > > +#define DWC_EQUALIZATION_DISABLE BIT(1) > > +#define DWC_EQ_PHASE_2_3_DISABLE BIT(2) > > + > > /* Synopsys-specific PCIe configuration registers */ > > #define PCIE_PORT_LINK_CONTROL 0x710 > > #define PORT_LINK_MODE_MASK GENMASK(21, 16) > > @@ -60,6 +64,10 @@ > > #define PCIE_MSI_INTR0_MASK 0x82C > > #define PCIE_MSI_INTR0_STATUS 0x830 > > > > +#define PCIE_PORT_GEN3_RELATED 0x890 > > +#define PORT_LOGIC_GEN3_EQ_PHASE_2_3_DISABLE BIT(9) > > +#define PORT_LOGIC_GEN3_EQ_DISABLE BIT(16) > > + > > #define PCIE_ATU_VIEWPORT 0x900 > > #define PCIE_ATU_REGION_INBOUND BIT(31) > > #define PCIE_ATU_REGION_OUTBOUND 0 > > @@ -253,6 +261,7 @@ struct dw_pcie { > > struct dw_pcie_ep ep; > > const struct dw_pcie_ops *ops; > > unsigned int version; > > + unsigned int quirk; > > }; > > > > #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, > > pp) > > -- > > 2.7.4 > >