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Sun, 09 Feb 2025 23:28:48 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 519NSlFf016355 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 9 Feb 2025 23:28:47 GMT Received: from [10.110.94.204] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 9 Feb 2025 15:28:46 -0800 Message-ID: <0636a261-f4db-4a62-b6f0-bee4f28c3a02@quicinc.com> Date: Sun, 9 Feb 2025 15:28:45 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/3] drm/msm/dsi: Set PHY usescase (and mode) before registering DSI host To: Marijn Suijten , Rob Clark , Dmitry Baryshkov , "Sean Paul" , David Airlie , Vinod Koul , Simona Vetter CC: , , , , "Jordan Crouse" , <~postmarketos/upstreaming@lists.sr.ht>, AngeloGioacchino Del Regno , "Martin Botka" , Jami Kettunen , Konrad Dybcio References: <20250209-drm-msm-initial-dualpipe-dsc-fixes-v2-0-9a60184fdc36@somainline.org> <20250209-drm-msm-initial-dualpipe-dsc-fixes-v2-2-9a60184fdc36@somainline.org> Content-Language: en-US From: Abhinav Kumar In-Reply-To: <20250209-drm-msm-initial-dualpipe-dsc-fixes-v2-2-9a60184fdc36@somainline.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 3Xy3RhDdrsw9yxHr7KT1tiLrtkPA01_e X-Proofpoint-GUID: 3Xy3RhDdrsw9yxHr7KT1tiLrtkPA01_e X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-09_10,2025-02-07_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 clxscore=1011 lowpriorityscore=0 impostorscore=0 mlxlogscore=927 mlxscore=0 priorityscore=1501 spamscore=0 adultscore=0 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502090209 On 2/9/2025 1:42 PM, Marijn Suijten wrote: > Ordering issues here cause an uninitialized (default STANDALONE) > usecase to be programmed (which appears to be a MUX) in some cases > when msm_dsi_host_register() is called, leading to the slave PLL in > bonded-DSI mode to source from a clock parent (dsi1vco) that is off. > > This should seemingly not be a problem as the actual dispcc clocks from > DSI1 that are muxed in the clock tree of DSI0 are way further down, this > bit still seems to have an effect on them somehow and causes the right > side of the panel controlled by DSI1 to not function. > > In an ideal world this code is refactored to no longer have such > error-prone calls "across subsystems", and instead model the "PLL src" > register field as a regular mux so that changing the clock parents > programmatically or in DTS via `assigned-clock-parents` has the > desired effect. > But for the avid reader, the clocks that we *are* muxing into DSI0's > tree are way further down, so if this bit turns out to be a simple mux > between dsiXvco and out_div, that shouldn't have any effect as this > whole tree is off anyway. > > Signed-off-by: Marijn Suijten > --- > drivers/gpu/drm/msm/dsi/dsi_manager.c | 30 +++++++++++++++++++----------- > 1 file changed, 19 insertions(+), 11 deletions(-) > Reviewed-by: Abhinav Kumar