From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752437AbcBJPVD (ORCPT ); Wed, 10 Feb 2016 10:21:03 -0500 Received: from smtp-out6.electric.net ([192.162.217.191]:65308 "EHLO smtp-out6.electric.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751111AbcBJPVA convert rfc822-to-8bit (ORCPT ); Wed, 10 Feb 2016 10:21:00 -0500 From: David Laight To: "'George Spelvin'" , "linux-kernel@vger.kernel.org" , "netdev@vger.kernel.org" , "tom@herbertland.com" CC: "mingo@kernel.org" Subject: RE: [PATCH v3 net-next] net: Implement fast csum_partial for x86_64 Thread-Topic: [PATCH v3 net-next] net: Implement fast csum_partial for x86_64 Thread-Index: AQHRYqy27Wbj7StuQUCi5Ndt7TrMLp8jhE3QgADxVwCAAK4CYIAAOdYAgAAEL7A= Date: Wed, 10 Feb 2016 15:18:14 +0000 Message-ID: <063D6719AE5E284EB5DD2968C1650D6D1CCDD01B@AcuExch.aculab.com> References: <063D6719AE5E284EB5DD2968C1650D6D1CCDCC8D@AcuExch.aculab.com> <20160210144334.23242.qmail@ns.horizon.com> In-Reply-To: <20160210144334.23242.qmail@ns.horizon.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.202.99.200] Content-Type: text/plain; charset="Windows-1252" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-Outbound-IP: 213.249.233.130 X-Env-From: David.Laight@ACULAB.COM X-PolicySMART: 3396946, 3397078 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: George Spelvin > Sent: 10 February 2016 14:44 ... > > I think the fastest loop is: > > 10: adcq 0(%rdi,%rcx,8),%rax > > inc %rcx > > jnz 10b > > That loop looks like it will have no overhead on recent cpu. > > Well, it should execute at 1 instruction/cycle. I presume you do mean 1 adc/cycle. If it doesn't unrolling once might help. > (No, a scaled offset doesn't take extra time.) Maybe I'm remembering the 386 book. > To break that requires ADCX/ADOX: > > 10: adcxq 0(%rdi,%rcx),%rax > adoxq 8(%rdi,%rcx),%rdx > leaq 16(%rcx),%rcx > jrcxz 11f > j 10b > 11: Getting 2 adc/cycle probably does require a little unrolling. With luck the adcxq, adoxq and leaq will execute together. The jrcxz is two clocks - so definitely needs a second adcoxq/adcxq pair. Experiments would be needed to confirm guesses though. David